Features: ·Fast match times: 3.5, 3.8, 4.0 and 4.5 ns
·Fast clock speed: 166, 150, 133, and 100 MHz
·Fast OE access times: 3.5, 3.8, 4.0 and 5.0 ns
·Pipelined data comparator
·Data input register load control by DEN
·Optimal for depth expansion (one cycle chip deselect to eliminate bus contention)
·3.3V -5% and +10% core power suppl
·2.5V or 3.3V I/O supply
·5V tolerant inputs except I/Os
·Clamp diodes to VSS at all inputs and outputs
·Common data inputs and data outputs
·JTAG boundary scan
·Byte Write Enable and Global Write control
·Three chip enables for depth expansion and address pipeline
·Address, data, and control registers
·Internally self-timed Write Cycle
·Burst control pins (interleaved or linear burst se-
quence)
·Automatic power-down for portable applications
·Low-profile JEDEC standard 100-pin TQFP packagePinout
SpecificationsVoltage on VCC Supply Relative to VSS..........-0.5V to +4.6V
VIN .........................................................-0.5V to VCC +0.5V
Storage Temperature (plastic) ................... -55 to +150
Junction Temperature ..............................................+150
Power Dissipation........................................................1.0W
Short Circuit Output Current......................................50 mADescriptionThe Cypress Synchronous Burst SRAM CY7C1359C/GVT71256T18 family employs high-speed, low power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high valued resistors.
All synchronous inputs of CY7C1359C/GVT71256T18 are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs of CY7C1359C/GVT71256T18 include all addresses, all data inputs, address-pipelin-ing Chip Enable (CE), depth-expansion Chip Enables (CE2and CE2), Burst Control Inputs (ADSC, ADSP, and ADV), WriteEnables (WEL, WEH, and BWE), Global Write (GW), and Data Input Enable (DEN).
Asynchronous inputs of CY7C1359C/GVT71256T18 include the Burst Mode Control (MODE), the Output Enable.(OE) and the Match Output Enable (MOE). The data outputs (Q) and Match Output (MATCH), enabled by (OE) and MOE respectively, are also asynchronous
Addresses and chip enables of CY7C1359C/GVT71256T18 are registered with either Address Status Processor (ADSP) or Address status Controller (ADSC) input pins. Subsequent burst addresses can be internally generated as controlled by the Burst Advance pin (ADV).
Data inputs of CY7C1359C/GVT71256T18 are registered with Data Input Enable (DEN) and chip enable pins (CE,CE2, and CE2). The outputs of the data input registers are compared with data in the memory array and a match signal is generated. The match output of CY7C1359C/GVT71256T18 is gated into a pipeline register and released to the match output pin at the next rising edge of Clock (CLK).
Address, data inputs, and write controls of CY7C1359C/GVT71256T18 are registered on-chip to initiate self-timed WRITE cycle. WRITE cycles can be one to two bytes wide as controlled by the write control inputs. Individual byte write allows individual byte to be written. WEL controls DQ1-DQ9. WEH controls DQ10-DQ18. WEL and WEH can be active only with BWE being LOW. GW being LOW causes all bytes to be written.
The CY7C1359C/GVT71256T18 operates from a +3.3V power supply with output power supply being +2.5V or +3.3V. All inputs and outputs are LVTTL compatible. The device is ideally suited for address tag RAM for up to 8 MB secondary cache.
GVT71256T18 Data Sheet
