GVT71128D32

The Galvantech Synchronous Burst SRAM familyemploys high-speed, low power CMOS designs usingadvanced triple-layer polysilicon, double-layer metaltechnology. Each memory cell consists of four transistors andtwo high valued resistors.

The GVT71128D32 SRAM integrates 131,072x32SRAM cells with advanced synchronous peripheral circuitryand a 2-bit counter for internal burst operation. Allsynchronous inputs are gated by registers controlled by apositive-edge-triggered clock input (CLK). The synchronousinputs include all addresses, all data inputs, address-pipeliningchip enable (CE#), depth-expansion chip enables (CE2# andCE2), burst control inputs (ADSC#, ADSP#, and ADV#),write enables (BW1#, BW2#, BW3#, BW4#,and BWE#), andglobal write (GW#).

Asynchronous inputs include the output enable (OE#)and burst mode control (MODE). The data outputs (Q),enabled by OE#, are also asynchronous.Addresses and chip enables are registered with eitheraddress status processor (ADSP#) or address status controller(ADSC#) input pins. Subsequent burst addresses can beinternally generated as controlled by the burst advance pin(ADV#).

Address, data inputs, and write controls are registered on-chip to initiate self-timed WRITE cycle. WRITE cycles canbe one to four bytes wide as controlled by the write controlnputs. Individual byte write allows individual byte to bewritten. BW1# controls DQ1-DQ8. BW2# controls DQ9-DQ16. BW3# controls DQ17-DQ24. BW4# controls DQ25-DQ32. BW1#, BW2# BW3#, and BW4# can be active onlywith BWE# being LOW. GW# being LOW causes all bytes tobe written. This device also incorporates pipelined enablecircuit for easy depth expansion without penalizing systemperformance.

The GVT71128D32 operates from a +3.3V powersupply. All inputs and outputs are TTL-compatible. Thedevice is ideally suited for 486, PentiumTM, 680x0, andPowerPCTM systems and for systems that are benefited from awide synchronous data bus.