Features: • Zero Bus Latency, no dead cycles between Write and Read cycles
• Fast clock speed: 200, 166, 133, 100 MHz
• Fast access time: 3.2, 3.6, 4.2, 5.0 ns
• Internally synchronized registered outputs eliminate the need to control OE
• Single 3.3V 5% and +5% power supply VCC
• Separate VCCQ for 3.3V or 2.5V I/O
• Single WEN (Read/Write) control pin
• Positive clock-edge triggered, address, data, and control signal registers for fully pipelined applications
• Interleaved or linear four-word burst capability
• Individual byte Write (BWaBWd) control (may be tied LOW)
• CEN pin to enable clock and suspend operations
• Three chip enables for simple depth expansion
• Automatic power-down feature available using ZZ mode or CE select
• JTAG boundary scan
• Low-profile 119-bump, 14-mm * 22-mm BGA (Ball Grid Array), and 100-pin TQFP packagesPinout
Specifications(Above which the useful life may be impaired. For user guidelines,not tested.)
Voltage on VCC Supply Relative to VSS ......... 0.5V to +4.6V
VIN ...........................................................0.5V to VCC+0.5V
Storage Temperature (plastic) ............... 55°C to +125°C
Junction Temperature ..............................................+125°C
Power Dissipation .........................................................2.0W
Short Circuit Output Current ....................................... 50 mA
Static Discharge Voltage ......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current ................................................... > 200 mADescriptionThe CY7C1354A/GVT71256ZC36 and CY7C1356A/GVT71512ZC18 SRAMs are designed to eliminate dead cycles when transitioning from Read to Write or vice versa. These SRAMs CY7C1354A/GVT71256ZC36 and CY7C1356A/GVT71512ZC18 are optimized for 100% bus utilization and achieve Zero Bus LatencyTM (ZBLTM)/No Bus LatencyTM (NoBLTM). They integrate 262,144 × 36 and 524,288 × 18 SRAM cells, respectively, with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. These employ high-speed, low-power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high-valued resistors.
All synchronous inputs of CY7C1354A/GVT71256ZC36 and CY7C1356A/GVT71512ZC18 are gated by registers controlled by a positive-edge-triggered clock input (CLK). The synchronous inputs of CY7C1354A/GVT71256ZC36 and CY7C1356A/GVT71512ZC18 include all addresses, all data inputs, depth-expansion Chip Enables (CE, CE2, and CE3), Cycle Start Input (ADV/LD), Clock Enable (CEN), Byte Write Enables (BWa, BWb, BWc,and BWd), and Read-Write Control (WEN). BWc and BWd apply to CY7C1354A/GVT71256ZC36 only.
Address and control signals are applied to the SRAM during one clock cycle, and two cycles later, CY7C1354A/GVT71256ZC36 and CY7C1356A/GVT71512ZC18's associated data occurs, either Read or Write.
A clock enable (CEN) pin allows operation of the CY7C1354A/GVT71256ZC36/CY7C1356A/GVT71512ZC18 to be suspended as long as necessary. All synchronous inputs are ignored when (CEN) is HIGH and the internal device registers will hold their previous values.
There are three chip enable pins (CE, CE2, CE3) that allow the user to deselect the CY7C1354A/GVT71256ZC36 and CY7C1356A/GVT71512ZC18 when desired. If any one of these three are not active when ADV/LD is LOW, no new memory operation can be initiated and any burst cycle in progress is stopped. However, any pending data transfers (Read or Write) will be completed. The data bus of CY7C1354A/GVT71256ZC36 and CY7C1356A/GVT71512ZC18 will be in high-impedance state two cycles after chip is deselected or a Write cycle is initiated.
The CY7C1354A/GVT71256ZC36 and CY7C1356A/GVT71512ZC18 have an on-chip two-bit burst counter. In the burst mode, the CY7C1354A/GVT71256ZC36 and CY7C1356A/GVT71512ZC18 provide four cycles of data for a single address presented to the SRAM. The order of the burst sequence is defined by the MODE input pin. The MODE pin selects between linear and interleaved burst sequence. The ADV/LD signal is used to load a new external address (ADV/LD = LOW) or increment the internal burst counter (ADV/LD = HIGH) Output Enable (OE), Sleep Enable (ZZ) and burst sequence select (MODE) are the asynchronous signals. OE can be used to disable the outputs at any given time. ZZ may be tied to LOW if it is not used.
Four pins are used to implement JTAG test capabilities. The JTAG circuitry is used to serially shift data to and from the device. JTAG inputs use LVTTL/LVCMOS levels to shift data during this testing mode of operation.
GVT71256ZC36 Data Sheet
