HCF4517B

Features: ` CLOCK FREQUENCY 12MHz (Typ.) at VDD = 10V` SCHMITT TRIGGER CLOCK INPUTS ALLOWS OPERATION WITH VERY SLOW CLOCK RISE AND FALL TIMES` THREE STATE OUTPUTS` QUIESCENT CURRENT SPECIFIED UP TO 20V` STANDARDIZED, SYMMETRICAL OUTPUT CHARACTERISTCS` 5V, 10V AND 15V PARAMETRIC RATINGS` INPUT LEAK...

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HCF4517B Picture
SeekIC No. : 004359710 Detail

HCF4517B: Features: ` CLOCK FREQUENCY 12MHz (Typ.) at VDD = 10V` SCHMITT TRIGGER CLOCK INPUTS ALLOWS OPERATION WITH VERY SLOW CLOCK RISE AND FALL TIMES` THREE STATE OUTPUTS` QUIESCENT CURRENT SPECIFIED UP TO ...

floor Price/Ceiling Price

Part Number:
HCF4517B
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/5/4

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Product Details

Description



Features:

` CLOCK FREQUENCY 12MHz (Typ.) at VDD = 10V
` SCHMITT TRIGGER CLOCK INPUTS ALLOWS OPERATION WITH VERY SLOW CLOCK RISE AND FALL TIMES
` THREE STATE OUTPUTS
` QUIESCENT CURRENT SPECIFIED UP TO 20V
` STANDARDIZED, SYMMETRICAL OUTPUT CHARACTERISTCS
` 5V, 10V AND 15V PARAMETRIC RATINGS
` INPUT LEAKAGE CURRENT
    II = 100nA (MAX) AT VDD = 18V TA = 25
` 100% TESTED FOR QUIESCENT CURRENT
` MEETS ALL REQUIREMENTS OF JEDEC JESD13B "STANDARD SPECIFICATIONS FOR DESCRIPTION OF B SERIES
   CMOS DEVICES"



Pinout

  Connection Diagram


Specifications

Symbol
Parameter
Value
Unit
VDD
Supply Voltage
-0.5 to +22
V
VI
DC Input Voltage
-0.5 to VDD + 0.5
V
II
DC Input Current
± 10
mA
PD
Power Dissipation per Package
200
mW
Power Dissipation per Output Transistor
100
mW
Top
Operating Temperature
-55 to +125
Tstg
Storage Temperature
-65 to +150
Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation under these conditions is not implied.

All voltage values are referred to VSS pin voltage.


Description

HCF4517B is a monolithic integrated circuit fabricated in Metal Oxide Semiconductor technology available in DIP package.

This HCF4517B is a dual 64-stage static shift register consisting of two independent registers each having a clock, data, and write enable input and outputs accessible by stages following the 16th, 32nd, 48th, and 64th stages. These stages also serve as input points allowing data to be put in at the 17th , 33rd, and 49th stages when the write enable input is a logic 1 and the clock goes through a low to high transition. The truth table indicates how the clock and write enable inputs control the operation of HCF4517B. Inputs at the intermediate stages allow entry of 64-bits into the register with 16 clock pulses. The 3-state outputs permit connection of this device to an external bus.




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