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Part Number: HCS74MS
Description: The Intersil HCS74MS is a Radiation Hardened positive edge triggered flip-flop with set and reset.
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HCS74MS
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Suppliers
DataSheet
General Description
HCS74MS General Description
The Intersil HCS74MS is a Radiation Hardened positive edge triggered flip-flop with set and reset.
The HCS74MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of radiation hardened, high-speed, CMOS/SOS Logic Family.
The HCS74MS is supplied in a 14 lead Ceramic flatpack (K suffix) or a SBDIP Package (D suffix).
HCS74MS Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to +7.0V
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VCC +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . .. . . . . .±10mA
DC Drain Current, Any One Output. . . . . . . . . . . . . . . .. . . . . .±25mA
(All Voltage Reference to the VSS Terminal)
Storage Temperature Range (TSTG). . . . . . . . .. . . . . -65 to +150
Lead Temperature (Soldering 10sec). . . . . . . . . . . . . . . . . . . . +265
Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175
ESD Classification . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . Class 1
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VCC +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . .. . . . . .±10mA
DC Drain Current, Any One Output. . . . . . . . . . . . . . . .. . . . . .±25mA
(All Voltage Reference to the VSS Terminal)
Storage Temperature Range (TSTG). . . . . . . . .. . . . . -65 to +150
Lead Temperature (Soldering 10sec). . . . . . . . . . . . . . . . . . . . +265
Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175
ESD Classification . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . Class 1
HCS74MS Features
* 3 Micron Radiation Hardened SOS CMOS
* Total Dose 200K RAD (Si)
* SEP Effective LET No Upsets: >100 MEV-cm2 /mg
* Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/Bit-Day (Typ)
* Dose Rate Survivability: >1 x 1012 RAD (Si)/s
* Dose Rate Upset >1010 RAD (Si)/s 20ns Pulse
* Latch-Up Free Under Any Conditions
* Military Temperature Range: -55 to +125
* Significant Power Reduction Compared to LSTTL ICs
* DC Operating Voltage Range: 4.5V to 5.5V
* Input Logic Levels
- VIL = 30% of VCC Max
- VIH = 70% of VCC Min
* Input Current Levels Ii 5A at VOL, VOH
* Total Dose 200K RAD (Si)
* SEP Effective LET No Upsets: >100 MEV-cm2 /mg
* Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/Bit-Day (Typ)
* Dose Rate Survivability: >1 x 1012 RAD (Si)/s
* Dose Rate Upset >1010 RAD (Si)/s 20ns Pulse
* Latch-Up Free Under Any Conditions
* Military Temperature Range: -55 to +125
* Significant Power Reduction Compared to LSTTL ICs
* DC Operating Voltage Range: 4.5V to 5.5V
* Input Logic Levels
- VIL = 30% of VCC Max
- VIH = 70% of VCC Min
* Input Current Levels Ii 5A at VOL, VOH
HCS74MS Connection Diagram
HCS74MS
PDF/DataSheet Download
- Datasheet: HCS74MS
- File Size: 179332 KB
- Manufacturer: Intersil
- Click here to Download
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IC CODE HOPPING DECODER 14-SOIC
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