Purchase HD6432138W, In-stock HD6432138W From SeekIC.
- Table of contents:
HD6432138W
-
Suppliers
DataSheet
General Description
HD6432138W Maximum Ratings
|
Item |
Symbol |
Value |
Unit |
| Power supply voltage |
VCC |
0.3 to +7.0 |
V |
| Input voltage (except ports 6 and 7) |
Vin |
0.3 to VCC +0.3 |
V |
| Input voltage (CIN input not selected for port 6) |
Vin |
0.3 to VCC +0.3 |
V |
| Input voltage (CIN input selected for port 6) |
Vin |
Lower voltage of 0.3 to VCC +0.3 and AVCC +0.3 |
V |
| Input voltage (port 7) |
Vin |
0.3 to AVCC + 0.3 |
V |
| Analog power supply voltage |
AVCC |
0.3 to +7.0 |
V |
| Analog input voltage |
VAN |
0.3 to AVCC + 0.3 |
V |
| Operating temperature |
Topr |
Regular specifications: 20 to +75* |
°C |
| Wide-range specifications: 40 to +85* | |||
| Operating temperature (flash memory programming/erasing) |
Topr |
Regular specifications: 0 to +75 |
°C |
| Wide-range specifications: 0 to +85 | |||
| Storage temperature |
Tstg |
55 to +125 |
°C |
HD6432138W Features
The H8S/2000 CPU has the following features.
` Upward-compatible with H8/300 and H8/300H CPUs
- Can execute H8/300 and H8/300H object programs
` General-register architecture
- Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit
registers)
` Sixty-five basic instructions
- 8/16/32-bit arithmetic and logic instructions
- Multiply and divide instructions
- Powerful bit-manipulation instructions
` Eight addressing modes
- Register direct [Rn]
- Register indirect [@ERn]
- Register indirect with displacement [@(d:16,ERn) or @(d:32,ERn)]
- Register indirect with post-increment or pre-decrement [@ERn+ or @ERn]
- Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32]
- Immediate [#xx:8, #xx:16, or #xx:32]
- Program-counter relative [@(d:8,PC) or @(d:16,PC)]
- Memory indirect [@@aa:8]
` 16-Mbyte address space
- Program: 16 Mbytes
- Data: 16 Mbytes (4 Gbytes architecturally)
` High-speed operation
- All frequently-used instructions execute in one or two states
- Maximum clock rate: 20 MHz
- 8/16/32-bit register-register add/subtract: 50 ns
- 8 * 8-bit register-register multiply: 600 ns
- 16 ÷ 8-bit register-register divide: 600 ns
- 16 *16-bit register-register multiply: 1000 ns
- 32 ÷ 16-bit register-register divide: 1000 ns
` Two CPU operating modes
- Normal mode
- Advanced mode
` Power-down state
- Transition to power-down state by SLEEP instruction
- CPU clock speed selection
` Upward-compatible with H8/300 and H8/300H CPUs
- Can execute H8/300 and H8/300H object programs
` General-register architecture
- Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit
registers)
` Sixty-five basic instructions
- 8/16/32-bit arithmetic and logic instructions
- Multiply and divide instructions
- Powerful bit-manipulation instructions
` Eight addressing modes
- Register direct [Rn]
- Register indirect [@ERn]
- Register indirect with displacement [@(d:16,ERn) or @(d:32,ERn)]
- Register indirect with post-increment or pre-decrement [@ERn+ or @ERn]
- Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32]
- Immediate [#xx:8, #xx:16, or #xx:32]
- Program-counter relative [@(d:8,PC) or @(d:16,PC)]
- Memory indirect [@@aa:8]
` 16-Mbyte address space
- Program: 16 Mbytes
- Data: 16 Mbytes (4 Gbytes architecturally)
` High-speed operation
- All frequently-used instructions execute in one or two states
- Maximum clock rate: 20 MHz
- 8/16/32-bit register-register add/subtract: 50 ns
- 8 * 8-bit register-register multiply: 600 ns
- 16 ÷ 8-bit register-register divide: 600 ns
- 16 *16-bit register-register multiply: 1000 ns
- 32 ÷ 16-bit register-register divide: 1000 ns
` Two CPU operating modes
- Normal mode
- Advanced mode
` Power-down state
- Transition to power-down state by SLEEP instruction
- CPU clock speed selection
HD6.8M50
PDF/DataSheet Download
- Datasheet: HD6.8M50
- File Size: 14795 KB
- Manufacturer: NTE [NTE Electronics]
- Click here to Download
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