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Part Number: HD6433064B
Description: Bits 6 to 4-Standby Timer Select 2 to 0 (STS2 to STS0): These bits select the length of time the CPU a...
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HD6433064B
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General Description
HD6433064B General Description
Bits 6 to 4-Standby Timer Select 2 to 0 (STS2 to STS0): These bits select the length of time the CPU and on-chip supporting modules wait for the internal clock oscillator to settle when software standby mode is exited by an external interrupt.
When using a crystal oscillator, set these bits so that the waiting time will be at least 7 ms at the system clock rate. When operating on an external clock, care is required in the case of the H8/3064F-ZTAT B-mask version, H8/3062F-ZTAT B-mask version, H8/3064 mask ROM Bmask version, H8/3062 mask ROM B-mask version, H8/3061 mask ROM B-mask version, and H8/3060 mask ROM B-mask version.
For further information about waiting time selection, see section 21.4.3, Selection of Waiting Time for Exit from Software Standby Mode.
HD6433064B Features
• Capability to process up to six pulse outputs or six pulse inputs
• Six general registers (GRs, two per channel) with independently-assignable output compare or input capture functions
• Selection of eight counter clock sources for each channel: Internal clocks: , /2, /4, /8 External clocks: TCLKA, TCLKB, TCLKC, TCLKD
• Five operating modes selectable in all channels:
--Waveform output by compare match Selection of 0 output, 1 output, or toggle output (only 0 or 1 output in channel 2)
--Input capture function Rising edge, falling edge, or both edges (selectable)
--Counter clearing function Counters can be cleared by compare match or input capture
--Synchronization Two or more timer counters (16TCNTs) can be preset simultaneously, or cleared simultaneously by compare match or input capture. Counter synchronization enables synchronous register input and output.
--PWM mode PWM output can be provided with an arbitrary duty cycle. With synchronization, up to three-phase PWM output is possible
• Phase counting mode selectable in channel 2 Two-phase encoder output can be counted automatically.
• High-speed access via internal 16-bit bus The 16TCNTs and GRs can be accessed at high speed via a 16-bit bus.
• Any initial timer output value can be set
• Nine interrupt sources Each channel has two compare match/input capture interrupts and an overflow interrupt. All interrupts can be requested independently.
• Six general registers (GRs, two per channel) with independently-assignable output compare or input capture functions
• Selection of eight counter clock sources for each channel: Internal clocks: , /2, /4, /8 External clocks: TCLKA, TCLKB, TCLKC, TCLKD
• Five operating modes selectable in all channels:
--Waveform output by compare match Selection of 0 output, 1 output, or toggle output (only 0 or 1 output in channel 2)
--Input capture function Rising edge, falling edge, or both edges (selectable)
--Counter clearing function Counters can be cleared by compare match or input capture
--Synchronization Two or more timer counters (16TCNTs) can be preset simultaneously, or cleared simultaneously by compare match or input capture. Counter synchronization enables synchronous register input and output.
--PWM mode PWM output can be provided with an arbitrary duty cycle. With synchronization, up to three-phase PWM output is possible
• Phase counting mode selectable in channel 2 Two-phase encoder output can be counted automatically.
• High-speed access via internal 16-bit bus The 16TCNTs and GRs can be accessed at high speed via a 16-bit bus.
• Any initial timer output value can be set
• Nine interrupt sources Each channel has two compare match/input capture interrupts and an overflow interrupt. All interrupts can be requested independently.
HD6433064B
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- Datasheet: HD6433064B
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