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Part Number: HD6433502
Description: The H8/3502 is a series of single-chip microcomputers integrating a CPU core together with a variety o...
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HD6433502
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General Description
HD6433502 General Description
The H8/3502 is a series of single-chip microcomputers integrating a CPU core together with a variety of peripheral functions needed in control systems.
The H8/300 CPU is a high-speed processor featuring powerful bit-manipulation instructions, ideally suited for realtime control applications. On-chip supporting modules necessary for system configuration include 16-kbyte ROM, 512-byte RAM, three types of timers (16-bit free-running timer, 8-bit timer, and watchdog timer), a serial communication interface (SCI), host interface (HIF), and I/O ports.
The H8/3502 can operate in single-chip mode or in two expanded modes, depending on the memory requirements of the application.
Development tools that support the functionally higher-end H8/3217 Series should be used for H8/3502 program development. As a ZTAT™ version, use the ZTAT™ version of the H8/3214.
Registers related to higher-level functions should not be accessed in this case. In particular, 1 must not be written in the IICS, IICX1, IICX0, SYNCE, PWCKE, and PWCKS bits in the serial/timer control register (STCR).
HD6433502 Maximum Ratings
| Item | Symbol | Rating | Unit |
| Supply voltage | VCC | 0.3 to +7.0 | V |
| Input voltage | Vin | 0.3 to VCC + 0.3 | V |
| Operating temperature | Topr | 20 to +75 | |
| Storage temperature | Tstg | 55 to +125 |
HD6433502 Features
CPU General register architecture
• Eight 16-bit general registers, or
• Sixteen 8-bit general registers
High speed
• Maximum clock rate: 10 MHz/5 V (ø clock)
• Add/subtract: 200 ns (10 MHz operation)
• Multiply/divide: 1400 ns (10 MHz operation)
Concise, streamlined instruction set
• All instructions are 2 or 4 bytes long
• Register-register arithmetic and logic operations
• Register-memory data transfer by MOV instruction
Instruction set features
• Multiply instruction (8 bits × 8 bits)
• Divide instruction (16 bits ÷ 8 bits)
• Bit-accumulator instructions
• Register-indirect specification of bit positions
Memory
• ROM: 16 kbytes
• RAM: 512 bytes
16-Bit free-running timer (FRT: 1 channel)
• One 16-bit free-running counter (also usable for external event counting)
• Two compare outputs
• One capture input
8-bit timer (TMR: 2 channels) Each channel has:
• One 8-bit up-counter (also usable for external event counting)
• Two time constant registers
Watchdog timer (WDT: 1 channel)
• Reset or NMI generation by overflow
• Can be switched to interval timer mode
Serial communication interface (SCI: 2 channels)
• Selection of asynchronous and synchronous modes
• Simultaneous transmit and receive (full duplex operation)
• On-chip baud rate generator
Host interface (HIF)
• 8-bit host interface port
• Three host interrupt requests (HIRQ1, HIRQ11, HIRQ12)
• Normal and fast A20 gate output
Keyboard controller
• Controls a matrix keyboard using a keyboard scan with wake-up interrupt and sense port configuration
• Two register sets (each comprising two data registers and a status register)
I/O ports
• 53 input/output pins (of which 24 can drive large current loads)
Interrupts
• Four external interrupt pins: NMI, IRQ0 to IRQ2
• Eight key-sense interrupt pins: KEYIN0 to KEYIN7
• Twenty-one on-chip interrupt sources
Operating modes
• Mode 1: expanded mode with on-chip ROM disabled
• Mode 2: expanded mode with on-chip ROM enabled
• Mode 3: single-chip mode
Power-down state
• Sleep mode
• Software standby mode
• Hardware standby mode
• Mode 3: single-chip mode
Other features
• On-chip clock oscillator
• Eight 16-bit general registers, or
• Sixteen 8-bit general registers
High speed
• Maximum clock rate: 10 MHz/5 V (ø clock)
• Add/subtract: 200 ns (10 MHz operation)
• Multiply/divide: 1400 ns (10 MHz operation)
Concise, streamlined instruction set
• All instructions are 2 or 4 bytes long
• Register-register arithmetic and logic operations
• Register-memory data transfer by MOV instruction
Instruction set features
• Multiply instruction (8 bits × 8 bits)
• Divide instruction (16 bits ÷ 8 bits)
• Bit-accumulator instructions
• Register-indirect specification of bit positions
Memory
• ROM: 16 kbytes
• RAM: 512 bytes
16-Bit free-running timer (FRT: 1 channel)
• One 16-bit free-running counter (also usable for external event counting)
• Two compare outputs
• One capture input
8-bit timer (TMR: 2 channels) Each channel has:
• One 8-bit up-counter (also usable for external event counting)
• Two time constant registers
Watchdog timer (WDT: 1 channel)
• Reset or NMI generation by overflow
• Can be switched to interval timer mode
Serial communication interface (SCI: 2 channels)
• Selection of asynchronous and synchronous modes
• Simultaneous transmit and receive (full duplex operation)
• On-chip baud rate generator
Host interface (HIF)
• 8-bit host interface port
• Three host interrupt requests (HIRQ1, HIRQ11, HIRQ12)
• Normal and fast A20 gate output
Keyboard controller
• Controls a matrix keyboard using a keyboard scan with wake-up interrupt and sense port configuration
• Two register sets (each comprising two data registers and a status register)
I/O ports
• 53 input/output pins (of which 24 can drive large current loads)
Interrupts
• Four external interrupt pins: NMI, IRQ0 to IRQ2
• Eight key-sense interrupt pins: KEYIN0 to KEYIN7
• Twenty-one on-chip interrupt sources
Operating modes
• Mode 1: expanded mode with on-chip ROM disabled
• Mode 2: expanded mode with on-chip ROM enabled
• Mode 3: single-chip mode
Power-down state
• Sleep mode
• Software standby mode
• Hardware standby mode
• Mode 3: single-chip mode
Other features
• On-chip clock oscillator
HD6.8M50
PDF/DataSheet Download
- Datasheet: HD6.8M50
- File Size: 14795 KB
- Manufacturer: NTE [NTE Electronics]
- Click here to Download
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