HI5634

Features:

• Pixel Clock Frequencies up to 250MHz
• Very Low Jitter
• Digital Phase Adjustment (DPA) for Clock Outputs
• Balanced PECL Differential Outputs
• Single-Ended SSTL_3 Clock Outputs
• Double-Buffered PLL/DPA Control Registers
• Independent Software Reset for PLL/DPA
• External or Internal Loop Filter Selection
• Uses 3.3V Supply. Inputs are 5V Tolerant.
• I2C-bus Serial Interface can Run at Either Low Speed (100kHz) or High Speed (400kHz)
• Lock Detection


Application

• LCD Monitors and Video Projectors
• Genlocking Multiple Video Subsystems
• Frequency Synthesis


Pinout




Specifications

VDDA, VDDD, VDDQ (Measured to V_SS) . . . . . . . . . . . . . . . 4.3V
Digital Inputs . . . . . . . . . . . . . .  . . . . . . . . VSSD -0.3V to +5.5V
Analog Outputs . . . . . . . . . . . . . . . . VSSA -0.3V to VDDA +0.3V
Digital Pouts. . . . . . . . . . . . . . . . . .. VSSQ -0.3V to VDDQ +0.3V
ESD Rating
Human Body Model (Per MIL-STD-883 Method 3015.7) . . . >2kV


Description

The HI5634 is a low cost but very high-performance frequency generator for line-locked and genlocked high resolution video applications. Utilizing an advanced low voltage CMOS mixed signal technology, the HI5634 is an effective clock solution for video projectors and displays at resolutions from VGA to beyond UXGA The HI5634 offers pixel clock outputs in both differential (to 250MHz) and single-ended (to 150MHz) formats. Digital phase adjustment circuitry allows user control of the pixel clock phase relative to the recovered sync signal. A second differential output at half the pixel clock rate enables deMUXing of multiplexed A/D converters. The FUNC pin provides either the regenerated input from the phase-locked loop (PLL) divider chain output or a re-synchronized and sharpened input HSYNC.

The HI5634 advanced PLL utilizes either its internal programmable feedback divider or an external divider. The device is programmed by a standard I2C-bus® serial interface.