HI5865

Features:

• Sampling Rate . . . . . . . . . . . . . . . . . . . . . . . . . 65 MSPS
• Low Power at 65 MSPS . . . . . . . . . . . . . . . . . . . .450mW
• Internal Sample and Hold
• Fully Differential Architecture
• Full Power Input Bandwidth . . . . . . . . . . . . . . . 250MHz
• Low Data Latency
• TTL Compatible Clock Input
• CMOS Compatible Digital Data Outputs


Application

• Multichannel Digital Communication Receivers
• Cellular/PCS Basestation Receivers
• Undersampling Digital IF
• Digital Subscriber Line (VDSL)
• Medical Ultrasound
• Reference Literature
      - AN9214, Using Harris High Speed A/D Converters


Pinout




Description

The HI5865 is a monolithic, 12-bit, 65 MSPS Analog-to-Digital Converter fabricated in an advanced CMOS process. It is designed for high speed, high resolution applications where wide bandwidth, low power consumption and excellent SINAD performance are essential. With a 250MHz full power input bandwidth and high frequency accuracy, the converter is ideal for many types of communication systems employing digital IF architectures.

The HI5865 is designed with a fully differential pipelined architecture using a front end differential-in-differential-out Sample-and-Hold amplifier (S/H). The HI5865 has excellent dynamic performance while consuming 450mW of power at 65 MSPS.Data output latches are provided which present valid data to the output bus with a low data latency of 9 clock cycles.