Features: · Processed with HVCMOS® technology· 32 push-pull CMOS output up to 32V· Low power level shifting· Source/sink current minimum 1mA· Shift register speed 5MHz· Latched data outputs· Bidirectional shift register (DIR)· Backplane outputPinoutSpecificationsSupply voltage, VDD2 -0.5V to +...
HV66: Features: · Processed with HVCMOS® technology· 32 push-pull CMOS output up to 32V· Low power level shifting· Source/sink current minimum 1mA· Shift register speed 5MHz· Latched data outputs· Bid...
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The HV66 is a low-voltage serial to high-voltage parallel converter with push-pull outputs. This device has been designed for use as a driver circuit for LCD displays. It can also be used in any application requiring multiple output high-voltage current sourcing and sinking capabilities. The inputs are fully CMOS compatible.
The device HV66 consists of a 32-bit shift register, 32 latches, and control logic to perform blanking and polarity control of the outputs. HVout1 is connected to the first stage of the shift register. Data is shifted through the shift register on the logic rising transition of the clock. A DIR pin causes data shifting counterclockwise when grounded and clockwise when connected to VDD. A data output buffer is provided for cascading devices. This output reflects the current status of the last bit of the shift register. Operation of the shift register is not affected by the LE (latch enable), BL (blank) or the POL (polarity) inputs. Transfer of data from the shift register to the latch occurs when the LE (latch enable) input is high. The data in the latch is stored after LE transitions from high to low.
The blank signal, BL, when pulled low, will set all outputs of HV66 to the same state as the BPOUT. If this signal is left open then the BL defaults to a high state.