HY57V121620(L)T

Features: • Single 3.3±0.3V power supply• All device pins are compatible with LVTTL interface• JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin pitch• All inputs and outputs referenced to positive edge of system clock • Data mask function by UDQM, LDQM• Int...

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HY57V121620(L)T Picture
SeekIC No. : 004368225 Detail

HY57V121620(L)T: Features: • Single 3.3±0.3V power supply• All device pins are compatible with LVTTL interface• JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin pitch• All inputs and out...

floor Price/Ceiling Price

Part Number:
HY57V121620(L)T
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/2/22

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Product Details

Description



Features:

• Single 3.3±0.3V power supply
• All device pins are compatible with LVTTL interface
• JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin pitch
• All inputs and outputs referenced to positive edge of system clock
• Data mask function by UDQM, LDQM
• Internal four banks operation
• Auto refresh and self refresh
• 8192 refresh cycles / 64ms
• Programmable Burst Length and Burst Type
   - 1, 2, 4, 8 or Full page for Sequential Burst
   - 1, 2, 4 or 8 for Interleave Burst
• Programmable CAS Latency ; 2, 3 Clocks



Pinout

  Connection Diagram


Specifications

Parameter
Symbol
Rating
Unit
Ambient Temperature TA
0 ~ 70
Storage Temperature TSTG
-55 ~ 125
Voltage on Any Pin relative to VSS VIN,VOUT
-1.0 ~ 4.6
V
Voltage on VDD relative to VSS VDD,VDDQ
-1.0 ~ 4.6
V
Short Circuit Output Current IOS
50
mA
Power Dissipation PD
1
W
Soldering Temperature ` Time TSOLER
260 ` 10
 ` Sec
Note : Operation at above absolute maximum rating can adversely affect device reliability


Description

The HY57V121620(L)T is a 512-Mbit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth. HY57V121620 is organized as 4banks of 8,388,608x16.

HY57V121620(L)T is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL.

Programmable options of HY57V121620(L)T include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)




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