HY57V561620CT-H

The HY57V561620CT-H belongs to the HY57V561620CT series. It is a kind of 4 Banks x 4 M x 16 bits synchronous DRAM. It is suitable for the main memoryapplications which require wide data I/O and high bandwidth. It includes fully synchronous operation referenced to a positive edge of the clock and it is available in the 400mil 54pin TSOP-II package which has 133 MHz clock frequency.

There are some HY57V561620CT-H features as follows. (1) all device pins are compatible with LVTTL interface; (2) all inputs and outputs referenced to positive edge of system clock; (3) data mask function by UDQM and LDQM; (4) internal four banks operation; (5) auto refresh and self refresh; (6) 8192 refresh cycles/64ms; (7) programmable burst length and burst type; (8) programmable CAS latency; (9) single 3.3 V±0.3 V power supply.

The following is some information about HY57V561620CT-H's absolute maximum ratings. (1): ambient temperature (TA) which is from 0 to 70 ; (2): storage temperature (TSTG) is from -55 to 125 ; (3): voltage on any pin relative to VSS (VIN,VOUT) is from -1.0 V to 4.6 V; (4): voltage on VDD relative to VSS (VDD) is from -1.0 V to 4.6 V; (5):
voltage on VDDQ relative to VSS (VDDQ) ranges from -1.0 V to 4.6 V; (6): short circuit output current (IOS) is 50 mA; (7): power dissipation (PD) is 1 W; (8): soldering temperature.time is 260.10 .sec; (9): the minimum input capacitance on CLK pin is 2.5 pF and the maximum is 3.5 pF; (10): the minimum data input/output capacitance on DQ1-DQ15 pin is 4.0 pF and the maximum is 6.5 pF.