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Part Number: HY5DS283222BFP
Description: The Hynix HY5DS283222 is a 134,217,728-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited...
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HY5DS283222BFP
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DataSheet
General Description
HY5DS283222BFP General Description
The Hynix HY5DS283222 is a 134,217,728-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the point-to-point applications which requires high bandwidth.
The Hynix 4Mx32 DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are inter- nally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible with SSTL_2.
HY5DS283222BFP Maximum Ratings
| Parameter | Symbol | Rating | Unit |
| Ambient Temperature |
TA |
0 ~ 70 |
oC |
| Storage Temperature | TSTG | -55 ~ 125 | oC |
| Voltage on Any Pin relative to VSS | VIN, VOUT | -0.5 ~ 3.6 | V |
| Voltage on VDD relative to VSS | VDD | -0.5 ~ 3.6 | V |
| Voltage on VDDQ relative to VSS | VDDQ | -0.5 ~ 3.6 | V |
| Output Short Circuit Current | IOS | 50 | mA |
| Power Dissipation | PD | 2 | W |
| Soldering Temperature . Time | TSOLDER | 260 . 10 | oC . sec |
HY5DS283222BFP Features
The Hynix HY5DS283222BF(P) guarantee until
166MHz speed at DLL_off condition
1.8V VDD and VDDQ wide range max power supply supports
All inputs and outputs are compatible with SSTL_2 nterface
12mm x 12mm, 144ball FBGA with 0.8mm pin pitch
Fully differential clock inputs (CK, /CK) operation
Double data rate interface
Source synchronous - data transaction aligned to
bidirectional data strobe (DQS0 ~ DQS3)
Data outputs on DQS edges when read (edged DQ)
Data inputs on DQS centers when write (centered DQ)
Data(DQ) and Write masks(DM) latched on the both
rising and falling edges of the data strobe
All addresses and control inputs except Data, Data
strobes and Data masks latched on the rising edges of the clock
Write mask byte controls by DM (DM0 ~ DM3)
Programmable /CAS Latency 5 / 4 supported
Programmable Burst Length 2 / 4 / 8 with both
sequential and interleave mode
Internal 4 bank operations with single pulsed /RAS
tRAS Lock-Out function supported
Auto refresh and self refresh supported 4096 refresh cycles / 32ms
Half strength and Matched Impedance driver option controlled by EMRS
166MHz speed at DLL_off condition
1.8V VDD and VDDQ wide range max power supply supports
All inputs and outputs are compatible with SSTL_2 nterface
12mm x 12mm, 144ball FBGA with 0.8mm pin pitch
Fully differential clock inputs (CK, /CK) operation
Double data rate interface
Source synchronous - data transaction aligned to
bidirectional data strobe (DQS0 ~ DQS3)
Data outputs on DQS edges when read (edged DQ)
Data inputs on DQS centers when write (centered DQ)
Data(DQ) and Write masks(DM) latched on the both
rising and falling edges of the data strobe
All addresses and control inputs except Data, Data
strobes and Data masks latched on the rising edges of the clock
Write mask byte controls by DM (DM0 ~ DM3)
Programmable /CAS Latency 5 / 4 supported
Programmable Burst Length 2 / 4 / 8 with both
sequential and interleave mode
Internal 4 bank operations with single pulsed /RAS
tRAS Lock-Out function supported
Auto refresh and self refresh supported 4096 refresh cycles / 32ms
Half strength and Matched Impedance driver option controlled by EMRS
HY5DS283222BFP Connection Diagram
HY5DS283222BFP-28
PDF/DataSheet Download
- Datasheet: HY5DS283222BFP-28
- File Size: 1032084 KB
- Manufacturer: HYNIX [Hynix Semiconductor]
- Click here to Download
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