Features: • Single 3.3±0.3V power supply• All device balls are compatible with LVTTL interface• 54Ball FBGA (10.5mm x 8.3mm)• All inputs and outputs referenced to positive edge of system clock• Data mask function by UDQM or LDQM• Internal four banks operation...
HY5V26CF: Features: • Single 3.3±0.3V power supply• All device balls are compatible with LVTTL interface• 54Ball FBGA (10.5mm x 8.3mm)• All inputs and outputs referenced to positive ed...
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Features: • JEDEC standard 3.3V power supply• All device pins are compatible with LVTT...
Symbol | Parameter | Rating | Unit |
VIN, VOUT | Voltage on Any ball relative to VSS | -0.3 to 3.0 | V |
VDD, VDDQ | Voltage on VDD relative to VSS | -1.0 ~ 4.6 | V |
IOS | Short Circuit Output Current | 50 | mA |
TA | Operating Temperature | 0 ~ 70 | |
TSTG | Storage Temperature | -55 ~ 125 | |
PD | Power Dissipation | 1.0 | W |
TSOLDER | Ball Soldering Temperature & Time | 260 ` 10 | `sec |
Note : Operation at above absolute maximum rating can adversely affect device reliability.
The Hynix HY5V26CF is a 134,217,728bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth. HY5V26C(L/S)F is organized as 4banks of 2,097,152x16 HY5V26C(L/S)F is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL.
HY5V26CF Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by a single control command (Burst length of 1,2,4,8, or full page), and the burst count sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)