HYB18L256169BF-7.5

Attention: Stresses above those listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit.

The HYB18L256169BF-7.5 is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits. It is internally configured as a quad-bank DRAM.

The HYB18L256169BF-7.5 achieves high speed data transfer rates by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to the system clock. Read and write accesses are urst-oriented; accesses start at a selected location and continue for a programmed number of locations (1, 2, 4, 8 or full page) in a programmed sequence.

The device HYB18L256169BF-7.5 operation is fully synchronous: all inputs are registered at the positive edge of CLK.

The HYB18L256169BF-7.5 is especially designed for mobile applications. It operates from a 1.8V power supply.

Power consumption in self refresh mode is drastically reduced by an On-Chip Temperature Sensor (OCTS); HYB18L256169BF-7.5 can rther be reduced by using the programmable Partial Array Self Refresh (PASR).

A conventional data-retaining Power-Down (PD) mode is available as well as a non-data-retaining Deep Power-Down (DPD) mode.

The HYB18L256169BF-7.5 is housed in a 54-ball PG-VFBGA package. It is available in Commercial (0 °C to 70 °C) and Extended (-25 °C to 85 °C) temperature range.