HYB18L512160BF-7.5

The HYB18L512160BF-7.5 is a high-speed CMOS, dynamic random-access memory containing 536,870,912 bits. It is internally configured as a quad-bank DRAM. The HY[B/E]18L512160BF achieves high speed data transfer rates by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to the system clock. Read and write accesses are burst-oriented. Accesses start at a selected location and continue for a programmed number of locations (1, 2, 4, 8 or full page) in a programmed sequence. The device operation is fully synchronous: all inputs are registered at the positive edge of CLK.

The HYB18L512160BF-7.5 is specially designed for mobile applications. It operates from a 1.8 V power supply. Power consumption in self refresh mode is drastically reduced by an On-Chip Temperature Sensor (OCTS); it can further be reduced by using the programmable Partial Array Self Refresh (PASR). A conventional data-retaining Power Down (PD) mode is available as well as a non-data-retaining Deep Power Down (DPD) mode. The HY[B/E]18L512160BF is housed in a Dual-Die 54-ball PG-TFBGA package.

HYB18L512160BF-7.5 is available in Commercial (0 to +70 ) and Extended (-25 to +85 ) temperature ranges.