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Part Number: IC42S16400A

 

 

 

 

Description: The IC42S16400A are high-speed 67,108,864-bit syn-chronous dynamic random-access memories, orga-nized as 1,048,576 x 16...


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IC42S16400A General Description


The IC42S16400A are high-speed 67,108,864-bit syn-chronous dynamic random-access memories, orga-nized as 1,048,576 x 16 x 4 (word x bit x bank), respectively.

The synchronous DRAMs achieved high-speed data transfer using the pipeline architecture and clock frequency up to 166MHz for -6. All input and outputs are synchronized with the positive edge of the clock.The synchronous DRAMs are compatible with Low Voltage TTL (LVTTL).These products are packaged in 54-pin TSOP-2 and 60ball(64M) VF-BGA.

IC42S16400A Features

• Single 3.3V (± 0.3V) power supply
• High speed clock cycle time -6: 166MHz, -7: 133MHz<3-3-3>
• Fully synchronous operation referenced to clock rising edge
• Possible to assert random column access in every cycle
• Quad internal banks contorlled by A12 & A13 (Bank Select)
• Byte control by LDQM and UDQM for IC42S16400A
• Programmable Wrap sequence (Sequential / Interleave)
• Programmable burst length (1, 2, 4, 8 and full page)
• Programmable CAS latency (2 and 3)
• Automatic precharge and controlled precharge
• CBR (Auto) refresh and self refresh
• LVTTL compatible inputs and outputs
• 4,096 refresh cycles / 64ms
• Burst termination by Burst stop and Precharge command
• Package 400mil 54-pin TSOP-2 and 60ball(64M) VF-BGA
• Pb(lead)-free package is available

IC42S16400A Connection Diagram

IC42S16400A  Connection Diagram

IC42S16400A datasheet

IC42S16400A-6BG
PDF/DataSheet Download

  • Datasheet: IC42S16400A-6BG
  • File Size: 1098260 KB
  • Manufacturer: ICSI [Integrated Circuit Solution Inc]
  • Click here to Download

Find IC42S16400A Suppliers

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IC42S16400A Relative Products

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    The IC42S16400 are high-speed 67,108,864-bit synchronous dynamic random-access memories, organized as 1,048,576 x 16 x 4 (word x bit x bank), respectively.The synchronous DRAMs of the IC42S16400 achieved high-speed data transfer using the pipeline architectu...

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