Features: • High-speed access time: 8, 10, 12, and 15 ns• CMOS low power operation• TTL compatible interface levels• Single 3.3V ± 10% power supply• Fully static operation: no clock or refresh required• Three state outputs• Data control for upper and lower...
IC61LV25616: Features: • High-speed access time: 8, 10, 12, and 15 ns• CMOS low power operation• TTL compatible interface levels• Single 3.3V ± 10% power supply• Fully static operat...
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ApplicationUsing this IC socket, developers can connect a 64-pin 0.8 mm-pitch LCC (64D0) package M...
Features: • High-speed access time: 12, 15, 20, 25 ns• Low active power: 600 mW (typic...

| Symbol | Parameter | Value | Unit |
| VTERM | Terminal Voltage with Respect to GND | 0.5 to Vcc+0.5 | V |
| TBIAS | Temperature Under Bias | 45 to +90 | |
| VCC | Vcc Related to GND | 0.3 to +4.0 | V |
| TSTG | Storage Temperature | 65 to +150 | |
| PT | Power Dissipation | 1.0 | W |
The ICSI IC61LV25616 is a high-speed, 4,194,304-bit static RAM organized as 262,144 words by 16 bits. It is fabricated using ICSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields high-performance and low power consumption devices. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels.
Easy memory expansion of the IC61LV25616 is provided by using Chip Enable and Output Enable inputs, CE and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access.
The IC61LV25616 is packaged in the JEDEC standard 44-pin 400mil SOJ, 44 pin 400mil TSOP-2 and 48-pin 6*8 TFBGA.