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ICS670-02

Features: • Packaged in 16-pin SOIC• Available in Pb (lead) free package• Clock inputs from 5 to 160 MHz (see page 2)• Patented PLL with low phase noise• Output clocks up to 160 MHz at 3.3 V• 15 selectable on-chip multipliers• Power down mode availableR...

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SeekIC No. : 004370877 Detail

ICS670-02: Features: • Packaged in 16-pin SOIC• Available in Pb (lead) free package• Clock inputs from 5 to 160 MHz (see page 2)• Patented PLL with low phase noise• Output clocks ...

ICS670-02 Data Sheet

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Part Number:
ICS670-02
Supply Ability:
5000

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  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

• Packaged in 16-pin SOIC
• Available in Pb (lead) free package
• Clock inputs from 5 to 160 MHz (see page 2)
• Patented PLL with low phase noise
• Output clocks up to 160 MHz at 3.3 V
• 15 selectable on-chip multipliers
• Power down mode available
• Low phase noise: -111 dBc/Hz at 10 kHz
• Output enable function tri-states outputs
• Low jitter 15 ps one sigma
• Advanced, low power, sub-micron CMOS process
• Operating voltage of 3.3 V or 5 V


Pinout

Connection Diagram


Specifications

Stresses above the ratings listed below can cause permanent damage to the ICS670-02. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range.
Item Rating
Supply Voltage, VDD 7 V
All Inputs and Outputs -0.5 V to VDD+0.5 V
Ambient Operating Temperature 0 to +70
Storage Temperature 65 to +150
Junction Temperature 150
Soldering Temperature 260



Description

The ICS670-02 is a high speed, low phase noise, Zero Delay Buffer (ZDB) which integrates ICS' proprietary analog/digital Phase Locked Loop (PLL) techniques. Part of ICS' ClockBlocksTM family, the part's zero delay feature means that the rising edge of the input clock aligns with the rising edges of the outputs giving the appearance of no delay through the device. There are two identical outputs on the chip. The FBCLK should be used to connect to the FBIN. Each output has its own output enable pin.

The ICS670-02 is ideal for synchronizing outputs in a large variety of systems, from personal computers to data communications to video. By allowing off-chip feedback paths, the chip can eliminate the delay through other devices. The 15 different on-chip multipliers work in a variety of applications. For other multipliers, including functional multipliers, see the ICS527.




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