ICS8431-21

Supply Voltage, VCC                                                  4.6V
Inputs, VI                                          -0.5V to VCC + 0.5V
Outputs, IO
Continuous Current                                                 50mA
Surge Current                                                        100mA
Package Thermal Impedance, JA       46.2°C/W (0 lfpm)
Storage Temperature, TSTG -65°C to                  150°C

NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.

The ICS8431-21 is a general purpose clock frequency synthesizer for IA64/32 application and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The VCO operates at a frequency range of 250MHz to 700MHz providing an output frequency range of 62.5MHz to 350MHz. The output frequency can be programmed using the parallel interface, M0 through M8 to the configuration logic, and the output divider control pin, DIV_SEL. Spread spectrum clocking is programmed via the control inputs SSC_CTL0 and SSC_CTL1.

Programmable features of the ICS8431-21 support four operational modes. The four modes are spread spectrum clocking (SSC), non-spread spectrum clock and two test modes which are controlled by the SSC_CTL[1:0] pins. Unlike other synthesizers, the ICS8431-21 can immediately change spread-spectrum operation without having to reset the device.

In SSC mode, the output clock of the ICS8431-21 is modulated in order to achieve a reduction in EMI. In one of the PLL bypass test modes, the PLL is disconnected as the source to the differential output allowing an external source to be connected to the TEST_I/O pin. This is useful for in-circuit testing and allows the differential output to be driven at a lower frequency throughout the system clock tree. In the other PLL bypass mode, the oscillator divider is used as the source to both the M and the Fout divide by 2. This is useful for characterizing the oscillator and internal dividers.  HiPerClockS™ ICS