ICS86953I-147

Features: • 9 single ended LVCMOS/LVTTL outputs;(8) clocks, (1) feedback• PCLK, nPCLK pair can accept the following differential input levels: LVPECL, CML, SSTL• Maximum output frequency: PLL Mode, 175MHz• VCO range: 250MHz to 700MHz• Output skew: 75ps (maximum)•...

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SeekIC No. : 004371084 Detail

ICS86953I-147: Features: • 9 single ended LVCMOS/LVTTL outputs;(8) clocks, (1) feedback• PCLK, nPCLK pair can accept the following differential input levels: LVPECL, CML, SSTL• Maximum output fre...

floor Price/Ceiling Price

Part Number:
ICS86953I-147
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2025/12/4

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Product Details

Description



Features:

• 9 single ended LVCMOS/LVTTL outputs;(8) clocks, (1) feedback
• PCLK, nPCLK pair can accept the following differential input levels: LVPECL, CML, SSTL
• Maximum output frequency: PLL Mode, 175MHz
• VCO range: 250MHz to 700MHz
• Output skew: 75ps (maximum)
• Cycle-to-cycle jitter: 50ps (maximum)
• Static phase offset: 90ps ± 110ps
• 3.3V supply voltage
• -40 to 85 ambient operating temperature
• Pin compatible to the MPC953



Pinout

  Connection Diagram


Specifications

Supply Voltage, VDD                                           4.6V
Inputs, VI                                     -0.5V to VDD+ 0.5 V
Outputs, VO                               -0.5V to VDDO + 0.5V
Package Thermal Impedance, JA   47.9/W (0 lfpm)
Storage Temperature, TSTG                  -65 to 150



Description

The ICS86953I-147 is a low voltage, low skew 1-to-9 Differential-to-LVCMOS/LVTTL Clock Generator and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The PCLK, nPCLK pair can accept most standard differential input levels. With output frequencies up to 175MHz, the ICS86953I-147 is targeted for high performance clock applications. Along with a fully integrated PLL, the ICS86953I-147 contains frequency configurable outputs and an external feedback input for regenerating clocks with "zero delay".




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