ICS8735-01

Features:

• 5 differential 3.3V LVPECL outputs
• Selectable differential clock inputs
• CLKx, nCLKx pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
• Output frequency range: 31.25MHz to 700MHz
• Input frequency range: 31.25MHz to 700MHz
• VCO range: 250MHz to 700MHz
• Programmable dividers allow for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
• External feedback for "zero delay" clock regeneration with configurable frequencies
• Cycle-to-cycle jitter: 25ps (maximum)
• Output skew: 25ps (maximum)
• Static phase offset: 50ps ± 100ps
• 3.3V supply voltage
• 0°C to 70°C ambient operating temperature
• Industrial temperature information available upon request


Pinout




Specifications

Supply Voltage, V_CC                               4.6V
Inputs, V_I                                               -0.5V to V_CC + 0.5 V
Outputs, V_O                                           -0.5V to V_CCO + 0.5V
Package Thermal Impedance, JA
32 Lead LQFP                                        47.9°C/W (0 lfpm)
32 Lead VFQFN                                      34.8°C/W (0 lfpm)
Storage Temperature, T_STG                   -65°C to 150°C
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.


Description

The ICS8735-01 is a highly versatile 1:5 Differential-to-3.3V LVPECL clock generator and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS8735-01 has a fully integrated PLL and can be configured as zero delay buffer, multiplier or divider, and has an output frequency range of 31.25MHz to 700MHz. The reference divider, feedback divider and output divider are each programmable, thereby allowing for the following output-toinput frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The external feedback allows the device to achieve "zero delay" between the input clock and the output clocks. The PLL_SEL pin can be used to bypass the PLL for system test and debug purposes. In bypass mode of the ICS8735-01, the reference clock is routed around the PLL and into the internal output dividers.