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IDT7019L

Features: M/S = VIH for BUSY output flag on Master, M/S = VIL for BUSY input on Slave Interrupt Flag On-chip port arbitration logic Full on-chip hardware support of semaphore signaling between ports Fully asynchronous operation from either port TTL-compatible, single 5V (±10%) power supply Availa...

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SeekIC No. : 004372005 Detail

IDT7019L: Features: M/S = VIH for BUSY output flag on Master, M/S = VIL for BUSY input on Slave Interrupt Flag On-chip port arbitration logic Full on-chip hardware support of semaphore signaling between port...

IDT7019L Data Sheet

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Part Number:
IDT7019L
Supply Ability:
5000

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  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

M/S = VIH for BUSY output flag on Master, M/S = VIL for BUSY input on Slave
Interrupt Flag
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling between ports
Fully asynchronous operation from either port
TTL-compatible, single 5V (±10%) power supply
Available in a 100-pin TQFP
Industrial temperature range (40°C to +85°C) is available for selected speeds
reads of the same memory location
High-speed access
Commercial: 15/20ns (max.)
 Low-power operation
IDT7019L
Active: 1W (typ.)
Standby: 1mW (typ.)
Dual chip enables allow for depth expansion without external logic
IDT7019 easily expands data bus width to 18 bits or more using the Master/Slave select when cascading more


Pinout

Connection Diagram
NOTES:
1. All Vcc pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. Package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part marking.


Specifications

Symbol
Rating
Com'l & Ind'l
Unit
Military
VTERM
Terminal Voltage
with respect to GND
0.5 to +4.5
V
 -0.5 to +7.0
TSTG
Temperature Under
Bias
55 to +125
°C
 -65 to +135
TSTG
Storage
Temperature
-65 to +150
mA
 -65 to +150
IOUT
DC Output Current
50
mA
50

NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect reliability.
2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of VTERM > Vcc + 10%.


Description

The IDT7019L is a high-speed 128K x 9 Dual-Port Static RAM. The IDT7019 is designed to be used as a stand-alone 1152K-bit Dual-Port RAM or as a combination MASTER/SLAVE Dual-Port RAM for 18-bit-ormore word systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 18-bit or wider memory system applications results in fullspeed, error-free operation without the need for additional discrete logic.

This IDT7019L provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down feature controlled by the chip enables (CE0 and CE1) permit the on-chip circuitry of each port to enter a very low standby power mode. Fabricated using IDT's CMOS high-performance technology, these devices typically operate on only1W of power. The IDT7019L is packaged in a 100-pin Thin Quad Flatpack (TQFP).




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