IDT7025S/L

Features:

True Dual-Ported memory cells which allow simultaneous reads of the same memory location
High-speed access
Military: 20/25/35/55/70ns (max.)
Industrial: 55ns (max.)
Commercial: 15/17/20/25/35/55ns (max.)
Low-power operation
IDT7025S
Active: 750mW (typ.)
Standby: 5mW (typ.)
IDT7025L
Active: 750mW (typ.)
Standby: 1mW (typ.)
Separate upper-byte and lower-byte control for multiplexed bus compatibility
using the Master/Slave select when cascading more than one device
M/S = H for BUSY output flag on Master M/S = L for BUSY input on Slave
Interrupt Flag
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling between ports
Fully asynchronous operation from either port
Battery backup operation-2V data retention
 TTL-compatible, single 5V (±10%) power supply
Available in 84-pin PGA, Flatpack, PLCC, and 100-pin Thin Quad Flatpack
Industrial temperature range (40°C to +85°C) is available for selected speeds


Pinout


NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. J84-1 package body is approximately 1.15 in x 1.15 in x .17 in.
F84-2 package body is approximately 1.17 in x 1.17 in x .11 in.
PN100-1 package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.


Specifications

Symbol	Rating	Com'l & Ind'l	Unit	Military
VTERM	Terminal Voltage with respect to GND	0.5 to +4.5	V	-0.5 to +7.0
TSTG	Temperature Under Bias	55 to +125	°C	-65 to +135
TSTG	Storage Temperature	-55 to +125	mA	-65 to +150
IOUT	DC Output Current	50	mA	50

NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns maximum, and is limited to < 20 mA for the period over VTERM > Vcc + 10%.


Description

The IDT7025S/L is a high-speed 8K x 16 Dual-Port Static RAM. The IDT7025 is designed to be used as a stand-alone 128K-bit Dual-Port RAM or as a combination MASTER/SLAVE Dual-Port RAM for 32-bit or more word systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 32-bit or wider memory system applications results in full-speed, errorfree operation without the need for additional discrete logic.

This IDT7025S/L provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down feature controlled by Chip Enable (CE) permits the on-chip circuitry of each port to enter a very low standby power mode. Fabricated using IDT's CMOS high-performance technology, these devices typically operate on only 750mW of power. Low-power (L) versions offer battery backup data retention capability with typical power consumption of 500µW from a 2V battery. The IDT7025 is packaged in a ceramic 84-pin PGA, an 84-pin Flatpack, PLCC, and a 100-pin TQFP. Military grade product is manufactured in compliance with the latest revision of MIL-PRF-38535 QML, making it ideally suited to military temperature applications demanding the highest level of performance and reliability.