IDT70V08S

Features:

 True Dual-Ported memory cells which allow simultaneous
    access of the same memory location
 High-speed access
    Commercial: 15/20/25/35ns (max.)
 Low-power operation
    IDT70V08S
        Active: 550mW (typ.)
        Standby: 5mW (typ.)
    IDT70V08L
        Active: 550mW (typ.)
        Standby: 1mW (typ.)
 Dual chip enables allow for depth expansion without
    external 
  IDT70V08 easily expands data bus width to 16 bits or
     more using the Master/Slave select when cascading more
     than one device
 M/S = V_IH for BUSY output flag on Master,
    M/S = V_IL forBUSY input on Slave
 Busy and Interrupt Flags
 On-chip port arbitration logic
 Full on-chip hardware support of semaphore signaling
    between ports
 Fully asynchronous operation from either port
 LVTTL-compatible, single 3.3V (±0.3V) power supply
 Available in a 100-pin TQFP
Industrial temperature range (40°C to +85°C) is available
    for selected speeds


Pinout




Specifications

Symbol	Rating	Commercial & Industrial	Unit
VTERM(2)	Terminal Voltage with Respect to GND	-0.5 to +4.6	V
TBIAS	Temperature Under Bias	-55 to +125	o C
TSTG	Storage Te mp e ra ture	-65 to +150	o C
IOUT	DC Output Current	50	mA

NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. VTERM must not exceed Vcc + 0.3V for more than 25% of the cycle time or 10ns maximum, and is limited to <  20mA for the period of VTERM > Vcc + 0.3V.

Description

The IDT70V08S is a high-speed 64K x 8 Dual-Port Static RAM.  The IDT70V08S is designed to be used as a stand-alone 512K-bit Dual-Port RAM or as a combination MASTER/SLAVE Dual-Port RAM for 16-bit-or-more word system. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 16-bit or wider memory system applications results in full-speed, error-free operation without the need for additional discrete logic.

This IDT70V08S provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down feature controlled by the  chip enables (either CE 0  or CE1) permit the on-chip circuitry of each port to enter a very low standby power mode.

Fabricated using IDT's CMOS high-performance technology, these devices typically operate on only 550mW of power.

The IDT70V08S is packaged in a 100-pin Thin Quad Flatpack (TQFP).