IDT70V17L

M/S = VIH for BUSY output flag on Master, M/S = VIL for BUSY input on Slave
Busy and Interrupt Flags
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling between ports
Fully asynchronous operation from either port
LVTTL-compatible, single 3.3V (±0.3V) power supply
Available in a 100-pin TQFP
Industrial temperature range (40°C to +85°C) is available for selected speeds
True Dual-Ported memory cells which allow simultaneous access of the same memory location
High-speed access
Commercial: 15/20ns (max.)
Industrial: 20ns (max.)
Low-power operation
IDT70V17L
Active: 440mW (typ.)
Standby: 660µW (typ.)
Dual chip enables allow for depth expansion without external logic
IDT70V17 easily expands data bus width to 18 bits or more using the Master/Slave select when cascading more than one device

NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. VTERM must not exceed VDD + 0.3V for more than 25% of the cycle time or 10ns maximum, and is limited to < 20mA for the period of VTERM > VDD + 0.3V. 5643 tbl