IDT70V658S

` True Dual-Port memory cells which allow simultaneous access of the same memory location
` High-speed access Commercial: 10/12/15ns (max.) Industrial: 12/15ns (max.)
` Dual chip enables allow for depth expansion without external logic
` IDT70V658 easily expands data bus width to 72 bits or more using the Master/Slave select when cascading more than one device
` M/S = VIH for BUSY output flag on Master, M/S = VIL for BUSY input on Slave
` Busy and Interrupt Flags
` On-chip port arbitration logic
` Full on-chip hardware support of semaphore signaling between ports
` Fully asynchronous operation from either port
` Separate byte controls for multiplexed bus and bus matching compatibility
` Supports JTAG features compliant to IEEE 1149.1
` LVTTL-compatible, single 3.3V (±150mV) power supply for core
` LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV) power supply for I/Os and control signals on each port
` Available in 208-pin Plastic Quad Flatpack, 208-ball fine pitch Ball Grid Array, and 256-ball Ball Grid Array
` Industrial temperature range (40°C to +85°C) is available for selected speeds

NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VTERM must not exceed VDD + 150mV for more than 25% of the cycle time or
4ns maximum, and is limited to < 20mA for the period of VTERM > VDD + 150mV.

The IDT70V658S is a high-speed 64K x 36 Asynchronous Dual-Port Static RAM. The IDT70V658S is designed to be used as a stand-alone 2304K-bit Dual-Port RAM or as a combination MASTER/SLAVE Dual- Port RAM for 72-bit-or-more word system. Using the IDT MASTER/ SLAVE Dual-Port RAM approach in 72-bit or wider memory system applications results in full-speed, error-free operation without the need for additional discrete logic.

This IDT70V658S provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down feature controlled by the chip enables (either CE0 or CE1) permit the on-chip circuitry of each port to enter a very low standby power mode.

The IDT70V658S can support an operating voltage of either 3.3V or 2.5V on one or both ports, controlled by the OPT pins. The power supply for the core of the device (VDD) remains at 3.3V.