IDT72V261LA

The IDT72261/72271 FIFOs have five flag functions, ,EF/,OR(Empty Flag or Output Ready), ,EE/,IR (Full Flag or Input Ready), and HF (Half-full Flag).  The ,EF and ,FF functions are selected in the IDT Standard Mode.

The  ,IR and ,EFOR functions are selected in the First Word Fall Through Mode.  ,IR indicates that the FIFO has free space to receive data.  ,OR indicates that data contained in the FIFO is available for reading.

,EFHF is a flag whose threshold is fixed at the half-way point in memory.  This flag can always be used  irrespective of mode.

,PAE, ,PAF can be programmed independantly to any point in memory.  They, also, can be used irrespective of mode. Programmable offsets determine the flag threshold and can be loaded by two methods: parallel or serial.  Two default offset settings are also provided, such that ,PAE can be set at
127 or 1023 locations from the empty boundary and the ,PAF threshold can be set at 127 or 1023 locations from the full boundary.  All these choices are made with,EFLD during Master Reset.

In the serial method, SEN together with LD are used to load the offset registers via the Serial Input (SI).  In the parallel method, ,WEN together with ,LD can be used to load the offset registers via Dn.  REN together with ,LD can be used to read the offsets in parallel from Qn regardless of whether serial or parallel offset loading is selected.

During Master Reset (,MRS), the read and write pointers are set to the first location of the FIFO.  The FWFT line selects IDT Standard Mode or FWFT Mode.  The ,LD pin selects  one of two partial flag default settings (127 or 1023) and, also, serial or parallel programming. The flags are updated accordingly.

The Partial Reset ,(PRS) also sets the read and write pointers to the first location of the memory.  However, the mode setting, programming method, and partial flag offsets are not altered. The flags are updated accordingly. ,PRS is useful for resetting a device in mid-operation, when reprogramming offset registers may not be convenient.

The Retransmit function allows data to be reread from the FIFO more than once.  A LOW on the RT input during a rising RCLK edge initiates aretransmit operation by setting the read pointer to the first location of the memory array.

If, at any time, the FIFO is not actively performing an operation, the chip will automatically power down. Once in the power down state, the standby
supply current consumption is minimized. Initiating any operation (by activating control inputs) will immediately take the device out of the power
down state.

The IDT72V261LA/72V271LA are fabricated using IDT's high speed submicron CMOS technology.