IDT72V71643

The IDT72V71643 has a maximum non-blocking switch capacity of 4,096 x 4,096 channels with data rates at 2.048 Mb/s, 4.096 Mb/s, 8.192 Mb/s or 16.384 Mb/s. With 32 inputs and 32 outputs, a variety of rate combinations is supported, under either Mux/Demux mode or Split mode, to allow for switching between streams of different data rates.

Output enable indications are provided through optional pins (one pin per output stream, only 16 output streams can be used in this mode) to facilitate external data bus control.

For applications requiring 32 streams and 32 per-stream Output Enable indicators, there is also an All Output Enable Feature.

The IDT72V71643 is capable of switching up to 4,096 x 4,096 channels without blocking. Designed to switch 64 Kbit/s PCM or N x 64 Kbit/s data, the device maintains frame integrity in data applications and minimizes throughput delay for voice applications on a per channel basis. The serial input streams (RX) and serial output streams (TX) of the IDT72V71643 can be run up to 16.384 Mb/s allowing 256 channels per 125s frame. Depending on the input and output data rates the device can support up to 32 serial streams.

With two main operating modes, Processor mode and Connection Mode, the IDT72V71643 can easily switch data from incoming serial streams (Data Memory) or from the controlling microprocessor (Connection Memory). As control and status information is critical in data transmission, the Processor mode is especially useful when there are multiple devices sharing the input and output streams.

With three main configuration modes, Regular, Mux/Demux, and Split mode the IDT72V71643 is designed to work in a mixed data-rate environment. In Mux/Demux mode, all of the input streams work at one data rate and the output streams at another. Depending on the configuration, more or less serial streams will be available on the inputs or outputs to maintain a non-blocking switch. In Split Mode, half of the input streams are set at one rate, while the other half are set to another rate. In this mode, both input and output streams are symmetrical. With data coming from multiple sources and through different paths, data entering the device is often delayed. To handle this problem, the IDT72V71643 has a frame evaluation feature to allow individual streams to be offset from the frame pulse in half clock-cycle intervals up to +4.5 clock cycles for speeds up to 8 Mb/s or +2.5 clock cycles for 16 Mb/s. (See Table 8 for maximum allowable skew).

The IDT72V71643 also provides a JTAG test access port, an internal loopback feature, memory block programming, a simple microprocessor interface and automatic ST-BUS®/GCI sensing to shorten setup time, aid in debugging and ease use of the device without sacrificing capabilities.