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Part Number: IDT74ALVC16260

 

 

 

 

Description: This 12-bit to 24-bit multiplexed D-type latch is built using advanced dual metal CMOS technology. The...


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IDT74ALVC16260 General Description


This 12-bit to 24-bit multiplexed D-type latch is built using advanced dual metal CMOS technology. The ALVC16260 is used in applications in which two separate data paths must be multiplexed onto, or demultiplexed from, a single data path. Typical applications include multiplexing and/or demultiplexing address and data information in microprocessor or bus-interface applications.

This device also is useful in memory interleaving applications. Three 12-bit I/O ports (A1-A12, 1B1-1B12, and 2B1-2B12) are available for address and/or data transfer. The output-enable (OE2B, OE2B, and OEA) inputs control the bus transceiver functions. The OE2B and OE2B control signals also allow bank control in the A-to-B direction. Address and/ or data information can be stored using the internal storage latches.

The latch-enable (LE1B, LE2B, LEA1B, and LEA2B) inputs are used to control data storage. When the latch-enable input is high, the latch is transparent. When the latch-enable input goes low, the data present at the inputs is latched and remains latched until the latch-enable input is returned high. The ALVC16260 has been designed with a ±24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance.

IDT74ALVC16260 Maximum Ratings

Symbol
Rating
Max
Unit
VTERM
(VDD)
VDD Terminal Voltage
with Respect to GND
0.5 to +4.6
V
VTERM(2)
VDDQ Terminal Voltage
with Respect to GND
0.5 to VCC+0.5
V
VTERM(2)
(INPUTS and I/O's)
Input and I/O Terminal
Voltage with Respect to GND
65 to +150
°C
IOUT
DC Output Current
50 to +50
°C
TSTG
Continuous Clamp Current,
VI < 0 or VI > VCC
-65 to +150
mA
TJN
Junction Temperature
+ 150
mA
IOK
Continuous Clamp Current, VO < 0
-50
mA
ICC
ISS
Continuous Current through
VCC or GND
±100
mA


1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. VCC terminals.
3. All terminals except VCC.

IDT74ALVC16260 Features

• 0.5 MICRON CMOS Technology
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0)
• VCC = 3.3V ± 0.3V, Normal Range
• VCC = 2.7V to 3.6V, Extended Range
• VCC = 2.5V ± 0.2V
• CMOS power levels (0.4µ W typ. static)
• Rail-to-Rail output swing for increased noise margin
• Available in SSOP, TSSOP, and TVSOP packages

IDT74ALVC16260 Typical Application

• 3.3V high speed systems
• 3.3V and lower voltage computing systems

IDT74ALVC16260 Connection Diagram

IDT74ALVC16260  Connection Diagram

IDT74ALVC16260 datasheet

IDT74ALVC16260
PDF/DataSheet Download

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