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Part Number: IDT74ALVC16835
Description: This 18-bit universal bus driver is built using advanced dual metal CMOS technology. Data flow from A ...
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IDT74ALVC16835
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General Description
IDT74ALVC16835 General Description
This 18-bit universal bus driver is built using advanced dual metal CMOS technology. Data flow from A to Y is controlled by the output-enable (OE) input. The device operates in the transparent mode when the latchenable (LE) input is high.
The A data is latched if the clock (CLK) input is held at a high or low logic level. If LE is low, the A data is stored in the latch flip-flop on the low-to-high transition of CLK. When OE is high, the outputs are in the high-impedance state. The ALVC16835 has been designed with a ±24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance.
IDT74ALVC16835 Maximum Ratings
|
Symbol |
Rating |
Max
|
Unit |
|
VTERM (VDD) |
VDD Terminal Voltage with Respect to GND |
0.5 to +4.6 |
V |
|
VTERM(2) |
VDDQ Terminal Voltage with Respect to GND |
0.5 to VCC+0.5 |
V |
|
VTERM(2) (INPUTS and I/O's) |
Input and I/O Terminal Voltage with Respect to GND |
65 to +150
|
°C |
|
IOUT |
DC Output Current |
50 to +50
|
°C |
|
TSTG |
Continuous Clamp Current, VI < 0 or VI > VCC |
-65 to +150
|
mA |
|
TJN |
Junction Temperature |
+ 150
|
mA |
|
IOK |
Continuous Clamp Current, VO < 0 |
-50
|
mA |
|
ICC ISS |
Continuous Current through VCC or GND |
±100
|
mA |
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. VCC terminals.
3. All terminals except VCC.
IDT74ALVC16835 Features
• 0.5 MICRON CMOS Technology
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0)
• VCC = 3.3V ± 0.3V, Normal Range
• VCC = 2.7V to 3.6V, Extended Range
• VCC = 2.5V ± 0.2V
• CMOS power levels (0.4µ W typ. static)
• Rail-to-Rail output swing for increased noise margin
• Available in SSOP, TSSOP, and TVSOP packages
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0)
• VCC = 3.3V ± 0.3V, Normal Range
• VCC = 2.7V to 3.6V, Extended Range
• VCC = 2.5V ± 0.2V
• CMOS power levels (0.4µ W typ. static)
• Rail-to-Rail output swing for increased noise margin
• Available in SSOP, TSSOP, and TVSOP packages
IDT74ALVC16835 Typical Application
• SDRAM Modules
• PC Motherboards
• Workstations
• PC Motherboards
• Workstations
IDT74ALVC16835 Connection Diagram
IDT74ALVC16835
PDF/DataSheet Download
- Datasheet: IDT74ALVC16835
- File Size: 65934 KB
- Manufacturer: IDT
- Click here to Download
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