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Part Number: IDT74ALVC32

 

 

 

 

Description: This quadruple 2-input positive-OR gate is built using ...


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IDT74ALVC32 General Description


This quadruple 2-input positive-OR gate is built using advanced dual metal CMOS technology. The ALVC32 performs the Boolean function Y = A • B or Y = A + B in positive logic.

The ALVC32 has been designed with a ±24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance.

IDT74ALVC32 Maximum Ratings

Symbol
Rating
Max
Unit
VTERM
(VDD)
VDD Terminal Voltage
with Respect to GND
0.5 to +4.6
V
VTERM(2)
VDDQ Terminal Voltage
with Respect to GND
0.5 to VCC+0.5
V
VTERM(2)
(INPUTS and I/O's)
Input and I/O Terminal
Voltage with Respect to GND
65 to +150
°C
IOUT
DC Output Current
50 to +50
°C
TSTG
Continuous Clamp Current,
VI < 0 or VI > VCC
-65 to +150
mA
TJN
Junction Temperature
+ 150
mA
IOK
Continuous Clamp Current, VO < 0
-50
mA
ICC
ISS
Continuous Current through
VCC or GND
±100
mA


NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. VCC terminals.
3. All terminals except VCC.

IDT74ALVC32 Features

• 0.5 MICRON CMOS Technology
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0)
• VCC = 3.3V ± 0.3V, Normal Range
• VCC = 2.7V to 3.6V, Extended Range
• VCC = 2.5V ± 0.2V
• CMOS power levels (0.4µ W typ. static)
• Rail-to-Rail output swing for increased noise margin
• Available in SOIC, SSOP, and TSSOP packages

IDT74ALVC32 Typical Application

• 3.3V high speed systems
• 3.3V and lower voltage computing systems

IDT74ALVC32 Connection Diagram

IDT74ALVC32  Connection Diagram

IDT74ALVC32 datasheet

IDT74ALVC32
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