IDT74FCT162701AT

The FCT162701T is an 18-bit Read/Write buffer with a four deep FIFO and a read-back latch. It can be used as a read/write buffer between a CPU and memory or to interface a high-speed bus and a slow peripheral. The A-to-B (write) path has a four deep FIFO for pipelined operations. The FIFO can be reset and a FIFO full condition is indicated by the full flag (FF). The B-to-A (read) path has a latch. A high on LE, allows data to flow transparently from B-to-A. A low on LE allows the data to be latched on the falling edge of LE.

The FCT162701T has a balanced output drive with series termination. This provides low ground bounce, minimal undershoot and controlled output edge rates.