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Part Number: IDT74FCT162701T
Description: The FCT162701T is an 18-bit Read/Write buffer with a four deep FIFO and a read-back latch. It can be u...
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IDT74FCT162701T
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General Description
IDT74FCT162701T General Description
The FCT162701T is an 18-bit Read/Write buffer with a four deep FIFO and a read-back latch. It can be used as a read/write buffer between a CPU and memory or to interface a high-speed bus and a slow peripheral. The A-to-B (write) path has a four deep FIFO for pipelined operations. The FIFO can be reset and a FIFO full condition is indicated by the full flag (FF). The B-to-A (read) path has a latch. A high on LE, allows data to flow transparently from B-to-A. A low on LE allows the data to be latched on the falling edge of LE.
The FCT162701T has a balanced output drive with series termination. This provides low ground bounce, minimal undershoot and controlled output edge rates.
IDT74FCT162701T Maximum Ratings
|
Symbol |
Description |
Max |
Unit |
|
VTERM(2) |
Terminal Voltage with Respect to GND |
0.5 to +7 |
V |
|
VTERM(3) |
Terminal Voltage with Respect to GND |
0.5 to VCC+0.5 |
V |
|
TSTG |
Storage Temperature |
65 to +150 |
°C |
|
IOUT |
DC Output Current |
60 to +120 |
mA |
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. All device terminals except FCT162XXX Output and I/O terminals.
3. Output and I/O terminals for FCT162XXX.
IDT74FCT162701T Features
• 0.5 MICRON CMOS Technology
• Typical tSK(o) (Output Skew) < 250ps
• Low input and output leakage 1A (max.)
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0)
• Balanced Output Drivers (±24mA)
• Reduced system switching noise
• Typical VOLP (Output Ground Bounce) < 0.6V at VCC = 5V, TA = 25°C
• Ideal for new generation x86 write-back cache solutions
• Suitable for modular x86 architectures
• Four deep write FIFO
• Latch in read path
• Synchronous FIFO reset
• Available in SSOP and TSSOP packages
• Typical tSK(o) (Output Skew) < 250ps
• Low input and output leakage 1A (max.)
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0)
• Balanced Output Drivers (±24mA)
• Reduced system switching noise
• Typical VOLP (Output Ground Bounce) < 0.6V at VCC = 5V, TA = 25°C
• Ideal for new generation x86 write-back cache solutions
• Suitable for modular x86 architectures
• Four deep write FIFO
• Latch in read path
• Synchronous FIFO reset
• Available in SSOP and TSSOP packages
IDT74FCT162701T Connection Diagram
IDT74FCT162701T
PDF/DataSheet Download
- Datasheet: IDT74FCT162701T
- File Size: 65396 KB
- Manufacturer: IDT
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