IDT74GTLP16612

The GTLP16612 is an 18-bit universal bus transceiver. It provides signal level translation, from TTL to GTLP, for applications requiring a highspeed interface between cards operating at TTL logic levels and backplanes operating at GTLP logic levels. GTLP provides reduced output swing (<1V), reduced input threshold levels, and output edge-rate control to minimize signal setting times. The GTLP16612 is a derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD8-3 and incorporates internal edge-rate control, which is process, voltage, and temperature (PVT) compensated.

GTLP output low voltage is less than 0.5V. The output high is 1.5V, and the receiver threshold is 1V.