IDT74LVC125APG

The IDT74LVC125APG is designed as quadruple bus buffer which is built using advanced dual metal CMOS technology. It features independent line drivers with 3-state outputs. Each output is disabled when the associated output enable input is high.

IDT74LVC125APG has nine features. (1)0.5 micron CMOS technology. (2)ESD>2000V per MIL-STD-883, method 3015;>200V using machine model (C=200pF, R=0). (3)Vcc=3.3V+/-0.3V normal range. (4)Vcc=2.7V to 3.6V extended range. (5)CMOS power levels (0.4uW typ static). (6)Rail-to-rail output swing for increased noise margin. (7)All inputs, outputs and I/Os are 5V tolerant. (8)Supports hot insertion. (9)Available in SOIC, SSOP and TSSOP packages. Those are all the main features.

Some absolute maximum ratings have been concluded into several points of IDT74LVC125APG as follow. (1)Its terminal voltage with respect to GND would be from -0.5V to 6.5V. (2)Its storage temperature range would be from -65°C to 150°C. (3)Its DC output current would be from -50mA to 50mA. (4)Its continuous clamp current would be -50mA. (5)Its continuous current through each Vcc or GND would be +/-100mA. It should be noted that stresses above those listed in absolute maximum ratings may cause permanent damage to device.

Also some electrical characteristics of IDT74LVC125APG are concluded as follow. (1)Its input high voltage level would be min 1.7V at Vcc=2.3V to 2.7V and would be min 2V at Vcc=2.7V to 3.6V. (2)Its input low voltage level would be max 0.7V at Vcc=2.3V to 2.7V and would be max 0.8V at Vcc=2.7V to 3.6V. (3)Its input leakage current would be max +/-5uA. (4)Its high impedance output current (3-state output pins) would be max +/-10uA. (5)Its input/output power off leakage would be max +/-50uA. (6)Its clamp diode voltage would be typ -0.7V and max -1.2V. (7)Its input hysteresis would be typ 100mV. And so on. If you have any question or suggestion or want to know more information please contact us for details. Thank you!