Features: • Functionality- Low speed to high speed SPI exchange device- Logical port (LP) mapping (SPI-3 <-> SPI-4) tables per direction- Per LP configurable memory allocation- Maskable interrupts for fatal errors- Fragment and burst length configurable per interface: min 16 bytes, max...
IDT88P8344: Features: • Functionality- Low speed to high speed SPI exchange device- Logical port (LP) mapping (SPI-3 <-> SPI-4) tables per direction- Per LP configurable memory allocation- Maskable ...
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| Parameter | Symbol | Conditions | Min.(1) | Max.(1) | Unit |
| Core Digital Supply Voltage | VDDC18 | VSS=0, AVSS=0, Tj=25°C | -0.3 | 2.2 | V |
| I/O Digital Supply Voltage | VDDT33 | -0.3 | 4.6 | V | |
| Analog Supply Voltage | VDDC18 | -0.3 | 3.6 | V | |
| Analog Supply Voltage | VDDT33 | -0.3 | 3.6 | V | |
| I/O Input Voltage for CMOS | VinL | -0.5 | 6.0 | V | |
| I/O Input Voltage for LVTTL | VinL | -0.5 | 6.0 | V | |
| I/O Output Voltage | Vout | -0.5 | 4.6 | V | |
| Latch-up Current | IO | - | 100 | mA | |
| ESD Performance (HBM) | - | 2000 | V | ||
| Ambient Operating Temperature | Ta(Industrial) | -40 | +85 | °C | |
| Ambient Operating Temperature | Ta(Commercial) | 0 | +70 | °C | |
| Storage Temperature | TS | -65 | +150 | °C |
The IDT88P8344 is a SPI (System Packet Interface) Exchange with four SPI- 3 interfaces and one SPI-4 interface. The data that enter on the low speed interface (SPI-3) are mapped to logical identifiers (LIDs) and enqueued for transmission over the high speed interface (SPI-4). The data that enter on the high speed interface (SPI-4) are mapped to logical identifiers (LIDs) and enqueued for transmission over a low speed interface (SPI-3). A data flow between SPI-3 and SPI-4 interfaces is accomplished with LID maps. The logical port addresses and number of entries in the LID maps may be dynamically configured. Various parameters of a data flow may be configured by the user such as buffer memory size and watermarks. In a typical application, the IDT88P8344 enables connection of multiple SPI-3 devices to a SPI-4 network processor. In other applications SPI-3 or SPI-4 devices may be connected to multiple SPI-3 network processors or traffic managers.