IP3023 Features
• 250 MIPS, 32-bit MASI CPU
• IP3023 is optimized for wireless networking
• 8-way simultaneous multithreading
• Deterministic execution on all threads
• Zero overhead full context switching
• Programmable MIPS per thread
• Optimized ISA for packet processing
• Memory to memory architecture, powerful addressing modes
• Small fast instruction set, strong bit manipulation
• Reduced code size vs RISC CPUs
• On-chip Program and Data memory
• Eliminates cache miss penalties
• 256KB (64k x 32) of Program SRAM
• 64kB (16k x 32) of Data SRAM
• Highly configurable I/O support
• Many Combinations of Software I/O:
• Utopia, PCMCIA, IDE/ATAPI
• PCM Highway, UART, SPI, I2C
• 32-bit 802.11a/g radios interface
• Two SerDes for fast serial I/O:
• 10Base-T (MAC/PHY), USB, GPSI
• SPI, UART, 2-wire serial, BlueRF
• Up to 4 MII ports for 10/100 PHY
• Additional key hardware
• True random number generator for software-implemented
encryption/security (32-bit seed)
• Fixed-point MAC (16x16+48-bit, 250 MMACs) for voice/audio
codecs, other signal processing tasks
• Independent I/O and core CPU clocking
• Separate Phase-Locked Loops (PLLs)
• Programmable multipliers & dividers
• Single low cost crystal (10MHz)
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