IS61DDB21M36

The 36Mb IS61DDB21M36 and IS61DDB22M18 are synchronous, high-performance CMOS static random access memory (SRAM) devices. These SRAMs have a common I/O bus. The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed.

Refer to the Timing Reference Diagram for Truth Table on page 8 for a description of the basic operations of these DDR-II (Burst of 2) CIO SRAMs.

The input addresses are registered on all rising edges of the K clock. The DQ bus operates at double data rate for reads and writes. The following are registered internally on the rising edge of the K clock:
• Read and write addresses
• Address load
• Read/write enable
• Byte writes
• Data-in

The following are registered on the rising edge of the K clock:
• Byte writes
• Data-in for second burst addresses

Byte writes can change with the corresponding datain to enable or disable writes on a per-byte basis. An internal write buffer enables the data-ins to be registered one cycle later than the write address. The first data-in burst is clocked with the rising edge of the next K clock, and the second burst is timed to the following rising edge of the K clock.

During the burst read operation, at the first burst the data-outs are updated from output registers off the second rising edge of the C clock (1.5 cycles later).

At the second burst, the data-outs are updated with the third rising edge of the corresponding C clock (see page 9). The K and K clocks are used to time the data-outs whenever the C and C clocks are tied high.

The device is operated with a single +1.8V power supply and is compatible with HSTL I/O interfaces.