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IS61LV12824

Features: • High-speed access time: 8, 10 ns• CMOS low power operation- 756 mW (max.) operating @ 8 ns- 36 mW (max.) standby @ 8 ns• TTL compatible interface levels• Single 3.3V power supply• Fully static operation: no clock or refresh required• Three state outp...

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SeekIC No. : 004379150 Detail

IS61LV12824: Features: • High-speed access time: 8, 10 ns• CMOS low power operation- 756 mW (max.) operating @ 8 ns- 36 mW (max.) standby @ 8 ns• TTL compatible interface levels• Single 3...

IS61LV12824 Data Sheet

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Part Number:
IS61LV12824
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

• High-speed access time: 8, 10 ns
• CMOS low power operation
- 756 mW (max.) operating @ 8 ns
- 36 mW (max.) standby @ 8 ns
• TTL compatible interface levels
• Single 3.3V power supply
• Fully static operation: no clock or refresh required
• Three state outputs
• Available in 119-pin Plastic Ball Grid Array (PBGA) and 100-pin TQFP packages.
• Industrial temperature available
• Lead-free available




Pinout






Specifications

Symbol Parameter
Value
Unit
VCC Power Supply Voltage Relative to GND
0.5 to +5.0
V
VTERM Terminal Voltage with Respect to GND
0.5 to VCC +0.5
V
TSTG Storage Temperature
65 to +150
TBIAS Temperature Under Bias: Com.
Ind.
10 to + 85
45 to +90

PT Power Dissipation
2.0
W
IOUT DC Output Current
±20
mA
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.




Description

The ISSI IS61LV12824 is a high-speed, static RAM organized as 131,072 words by 24 bits. It is fabricated using ISSI's highperformance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields access times as fast as 8 ns with low power consumption.

When CE1,CE2 are HIGH and CE2 is LOW (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels.

Easy memory expansion is provided by using Chip Enable and Output Enable inputs, CE1, CE2,CE2 and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory.

The IS61LV12824 is packaged in the JEDEC standard 119-pin PBGA and 100-pin TQFP






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