IS61LV6432

Features:

* Internal self-timed write cycle
* Individual Byte Write Control and Global Write
* Clock controlled, registered address, data and control
* Pentium(TM) or linear burst sequence control using MODE input
* Three chip enables for simple depth expansion and address pipelining
* Common data inputs and data outputs
* Power-down control by ZZ input
* JEDEC 100-Pin LQFP and PQFP package
* 3.3V VCC and 2.5V VCCQ for 2.5 I/O's
* Two Clock enables and one Clock disable to eliminate multiple bank bus contention.
* Control pins mode upon power-up:
     MODE in interleave burst mode
     ZZ in normal operation mode
   These control pins can be connected to GNDQ or VCCQ to alter their power-up state
* Industrial temperature available


Pinout




Specifications

Symbol	Parameter	Value	Unit
TBIAS	Temperature Under Bias	10 to +85	°C
TSTG	Storage Temperature	55 to +150	°C
PD	Power Dissipation	1.8	W
IOUT	Output Current (per I/O)	100	mA
VIN, VOUT	Voltage Relative to GND for I/O Pins	0.5 to VCCQ + 0.3	V
VIN	Voltage Relative to GND for for Address and Control Inputs	0.5 to 4.6	V

 


Description

The ICSI IS61LV6432 is a high-speed, low-power synchro- nous static RAM designed to provide a burstable, high-perfor- mance, secondary cache for the Pentium(TM), 680X0(TM), and PowerPC(TM) microprocessors.  It is organized as 65,536 words by 32 bits, fabricated with ICSI's advanced CMOS technology.
The device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input.

Write cycles are internally self-timed and are initiated by the rising edge of the clock input. Write cycles can be from one to four bytes wide as controlled by the write control inputs.