IS61NLP25672-200B1I

The IS61NLP25672-200B1I is one member of the IS61NLP series.The SRAM can operate without using the JTAG feature.To disable the TAP controller,TCK must be tied LOW (VSS) to prevent clocking of the device.TDI and TMS are internally pulled up and may be disconnected. They may alternately be connected to VDD through a pull-up resistor.TDO should be left disconnected.On power-up,the device will start in a reset state which will not interfere with the device operation.

Features of the IS61NLP25672-200B1I are:(1)100 percent bus utilization; (2)no wait cycles between read and write; (3)internal self-timed write cycle; (4)individual byte write control; (5)single r/w (read/write) control pin; (6)clock controlled, registered address, data and control; (7)interleaved or linear burst sequence control using mode input; (8)three chip enables for simple depth expansion and address pipelining; (9)power down mode; (10)common data inputs and data outputs; (11)JTAG boundary scan for PBGA packages; (12)industrial temperature available; (13)lead-free available.The Boundary Scan Order tables show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package.The MSB of the register is connected to TDI, and the LSB is connected to TDO.

The absolute maximum ratings of the IS61NLP25672-200B1I can be summarized as:(1)power dissipation:1.6 W;(2)storage temperature:-65 to 150;(3)output current (per I/O):100 mA;(4)voltage relative to VSS for I/O pins:0.5 to VDDQ + 0.3 V;(5)voltage relative to VSS for address and control inputs:0.3 to 4.6 V.Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.The TDI pin is used to serially input information to the registers and can be connected to the input of any register. The register between TDI and TDO is chosen by the instruction loaded into the TAP instruction register.