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IS75V16F128GS32

Features: • Power supply voltage 2.7V to 3.3V• High performance: Flash: 70ns maximum access time PSRAM: 65ns maximum access time• Package: 107-ball BGA• Operating Temperature: -30C to +85C• Power Dissipation: Read Current at 1 Mhz: 4 mA maximum Read Current at 5 Mhz:1...

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SeekIC No. : 004379316 Detail

IS75V16F128GS32: Features: • Power supply voltage 2.7V to 3.3V• High performance: Flash: 70ns maximum access time PSRAM: 65ns maximum access time• Package: 107-ball BGA• Operating Temperature...

IS75V16F128GS32 Data Sheet

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Part Number:
IS75V16F128GS32
Supply Ability:
5000

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  • 1~5000
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  • Negotiable
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  • 15 Days
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Product Details

Description



Features:

•   Power supply voltage 2.7V to 3.3V
• High performance:
   Flash: 70ns maximum access time
   PSRAM: 65ns maximum access time
• Package: 107-ball BGA
• Operating Temperature: -30C to +85C
• Power Dissipation:
   Read Current at 1 Mhz: 4 mA maximum
   Read Current at 5 Mhz:18 mA maximum
   Sleep Mode: 5 A maximum
• User Configurable Banks
   Flash 1 (64 Mbit)
   Bank A1: 8Mbit (8KB x 8 and 64KB x 15)
   Bank B1: 24Mbit (64KB x 48)
   Bank C1: 24Mbit (64KB x 48)
   Bank D1: 8Mbit (8KB x 8 and 64KB x 15)
   Flash 2 (64 Mbit)
   Bank A2: 8Mbit (8KB x 8 and 64KB x 15)
   Bank B2: 24Mbit (64KB x 48)
   Bank C2: 24Mbit (64KB x 48)
   Bank D2: 8Mbit (8KB x 8 and 64KB x 15)
   User chooses two virtual banks from a combination of four physical banks
• Simultaneous R/W Operations (dual virtual bank):
   Zero latency between read and write operations; Data can be programmed or erased in one bank while data is simultaneously being read from the other bank
• Low-Power Mode:
   A period of no activity causes flash to enter a low-power state
• Erase Suspend/Resume:
   Suspends of erase activity to allow a read in the same bank
• Sector Erase Architecture:
   16 sectors of 4K words each and 126 sectors of 32K words each in Word mode. Any combination of sectors, or the entire flash can be simultaneously erased
• Erase Algorithms:
   Automatically preprograms/erases the flash memory entirely, or by sector
• Program Algorithms:
   Automatically writes and verifies data at specified address
• Hidden ROM Region:
   256 byte with a Factory-serialized secure electronic serial number (ESN), which is accessible through a command sequence
• Data Polling and Toggle Bit:
   Detects the completion of the program or erase cycle
• Ready-Busy Outputs (RY/BY)
   Detection of program or erase cycle completion for each flash chip
• Over 100,000 write/erase cycles
• Low supply voltage (Vccf 2.5V) inhibits writes
• WP/ACC input pin:
   If VIL, allows partial protection of boot sectors
   If VIH, allows removal of boot sector
• Power Dissipation:
   Operating: 25 mA maximum
   Standby: 110 A maximum
• Chip Selects: CE1r, CE2r
• Power down feature using CE2r
   Sleep Mode: 10 A maximum
   Nap: 65 A maximum
8 mbit Partial: 80 A maximum
• Data retention supply voltage: 2.1 V to 3.3V
• Byte data control: LB (DQ0DQ7),UB (DQ8DQ15)


Specifications

Symbol Parameter
Rating
Unit
Min.
Max.
Tstg Storage Temperature
-55
+125
TA Ambient Temperature with Power Applied
-30
+85
VIN,VOUT Voltage with Respect to Ground All Pins(2)
-0.3
VCC+0.3(6)
V
VCCf1,VCCf2 VCCf Supply(2)
-0.3
3.5
V
VCCr VCCr Supply(2)
-0.3
3.5
V
VIN RESET1, RESET2(3)
-0.5
+13.0
V
VACC WP/ACC(4)
-0.5
+10.5
V
Notes:
1. Voltage is defined on the basis of GND = 0 V.
2. Minimum DC voltage on input or I/O pins is -0.3 V. During voltage transitions, input or I/O pins may undershoot GND to -1.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCCf1+ 0.3V , VCCf2+ 0.3V or VCCr + 0.3 V. During voltage transitions, input or I/O pins may overshoot to VCCf1+ 2.0V , VCCf2+ 2.0 V or VCCr + 1.0 V for periods of up to 20 ns.
3. Minimum DC input voltage on RESET1 or RESET2 pin is -0.5 V. During voltage transitions, RESET1 or RESET2 pin may
undershoot GND to -2.0 V for periods of up to 20 ns.
   The voltage difference between input and supply voltage (VIN-VCCf1 or VCCf2) does not exceed 9.0 V.
   The maximum DC input voltage on the RESET pin is +13.0 V that may overshoot to +14.0 V for periods of up to 20 ns.
4. Minimum DC input voltage on WP/ACC pin is -0.5 V. During voltage transitions, WP/ACC pin may undershoot GND to -2.0 V for periods of up to 20 ns. Maximum DC input voltage on WP/ACC pin is +10.5 V which may overshoot to +12.0 V for periods of up to 20 ns, when VCCf1 or VCCf2 is applied.
5. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
6. This Vcc refers to the minimum of VCCf1, VCCf2, or Vccr .


Description

This 107-ball MCP IS75V16F128GS32 is a space-saving combination of 3 memories: two 64Mbit Flash and one 32Mbit Pseudo SRAM. Each 64Mbit Flash (Flash1 and Flash 2) contains 4,194,304 words and the 32Mbit PSRAM contains 2,097,152 words. Each word is 16 bits wide. Data lines DQ0-DQ15 handle the access for all three memories. Write Enable,Output Enable, and A0-A20 are shared among the three memories. Single Byte data on the PSRAM can be accessed one at a time on DQ0-DQ7 or DQ8-DQ15 by using LB or UB, respectively.  The package of IS75V16F128GS32 uses a 3.0V power supply for all operations. No other source is required for program and erase  perations.

The flash IS75V16F128GS32 can be programmed in system using this 3.0V supply, or can be programmed in a standard EPROM programmer.

The flash chips IS75V16F128GS32 are compatible with the JEDEC Flash command set standard. The flash access time is 70ns and the PSRAM access time is 65ns.

Each Flash memory implements an architecture composed of two virtual banks that allows simultaneous operation on
each bank. Optimized performance can be achieved by first initializing a program or erase function in one bank, then
immediately starting a read from the other bank. Both operations would then be operating simultaneously on the same chip, with zero latency.




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