ISP1761 Selling Leads, Price trend, ISP1761 DataSheet download, circuit diagram from SeekIC.com

Features: ` Compliant with Universal Serial Bus Specification Rev. 2.0; supporting data transfer at high-speed (480 Mbit/s), full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s)` Integrated Transaction Translator (TT) for Original USB (full-speed and low-speed) peripheral support` Three USB ports tha...

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Features:

` Compliant with Universal Serial Bus Specification Rev. 2.0; supporting data transfer at high-speed (480 Mbit/s), full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s)
` Integrated Transaction Translator (TT) for Original USB (full-speed and low-speed) peripheral support
` Three USB ports that support three operational modes:
   ` Mode 1: Port 1 is an OTG Controller port, and ports 2 and 3 are Host Controller ports
   ` Mode 2: Ports 1, 2 and 3 are Host Controller ports
   ` Mode 3: Port 1 is a Peripheral Controller port, and ports 2 and 3 are Host Controller ports
` Supports OTG Host Negotiation Protocol (HNP) and Session Request Protocol (SRP)
` Multitasking support with Virtual Segmentation feature (up to four banks)
` High-speed memory controller (variable latency and SRAM external interface)
` Directly addressable memory architecture
` Generic processor interface to most CPUs, such as: Hitachi^® SH-3 and SH-4, Philips XA, Intel^® StrongARM^®, NEC^® and Toshiba^® MIPS, Motorola^® DragonBall™ and PowerPC^® Reduced Instruction Set Computer (RISC) processors
` Configurable 32-bit and 16-bit external memory data bus
` Supports Programmed I/O (PIO) and Direct Memory Access (DMA)
` Slave DMA implementation on CPU interface for reducing the host system's CPU load
_` Separate IRQ, DREQ and DACK lines for the Host Controller and the Peripheral Controller
_` Integrated multiconfiguration FIFO
_` Double-buffering scheme increases throughput and facilitates real-time data transfer
_` Integrated Phase-Locked Loop (PLL) with external 12 MHz crystal for low EMI
_` Tolerant I/O for low voltage CPU interface (1.65 V to 3.3 V)
_` 3.3 V-to-5.0 V external power supply input
_` Integrated 5.0 V-to-1.8 V or 3.3 V-to-1.8 V voltage regulator (internal 1.8 V for low-power core)
_` Internal power-on reset or low-voltage reset and block-dedicated software reset
_` Supports suspend and remote wake-up
_` Built-in overcurrent circuitry (analog overcurrent protection)
_` Hybrid-power mode: V_CC(5V0) (can be switched off), V_CC(I/O) (permanent)
_` Target total current consumption:
   _` Normal operation; one port in high-speed active: I_CC < 100 mA when the internal charge pump is not used
   _` Suspend mode: I_CC(susp) < 150 A at the room temperature
_` Available in LQFP128 and TFBGA128 packages
_` Host Controller-specific features
   _` High performance USB host with integrated high-speed USB transceivers;supports high-speed, full-speed and low-speed
   _` The EHCI core is adapted from Enhanced Host Controller Interface Specification for Universal Serial Bus Rev. 1.0
   _` Configurable power management
   _` Integrated TT for Original USB peripheral support on all three ports
   _` Integrated 64 kB high-speed memory (internally organized as 8 k X 64 bits)
   _` Additional 2.5 kB separate memory for TT
   _` Individual or global overcurrent protection with built-in sense circuits
   _` Overcurrent circuitry built-in (digital or analog overcurrent protection)
_` OTG Controller-specific features
   _` OTG transceiver: fully integrated; compliant with On-The-Go Supplement to the
   _`SB Specification Rev. 1.0a
   _` Supports HNP and SRP for OTG dual-role devices
   _` HNP: status and control registers for software implementation
   _`SRP: status and control registers for software implementation
   _` Programmable timers with high resolution (0.01 ms to 80 ms)-for HNP and SRP
   _` Supports external source of V_{BUS
   `_{Peripheral Controller-specific features
_` High-performance USB Peripheral Controller with integrated Serial Interface Engine (SIE), FIFO memory and transceiver
_` Complies with Universal Serial Bus Specification Rev. 2.0 and most device class specifications
   _` Supports auto Hi-Speed USB mode discovery and Original USB fallback capabilities
_` Supports high-speed and full-speed on the Peripheral Controller
_` Bus-powered or self-powered capability with suspend mod
_` Slave DMA, fully autonomous and supports multiple configurations
_` Seven IN endpoints, seven OUT endpoints and one fixed control IN and OUT
endpoint
_` Integrated 8 kB memory
_` Software-controllable connection to the USB bus, SoftConnect™}}

Application

· Mobile phone to/from:
   · Mobile phone: exchange contact information
   · Digital still camera: e-mail pictures or upload pictures to the web
   · MP3 player: upload/download/broadcast music
   · Mass storage: upload/download files
   · Scanner: scan business cards
· Digital still camera to/from:
   · Digital still camera: exchange pictures
   · Mobile phone: e-mail pictures, upload pictures to the web
   · Printer: print pictures
   · Mass storage: store pictures
· Printer to/from:
   · Digital still camera: print pictures
   · Scanner: print scanned image
   · Mass storage: print files stored in a device
· MP3 player to/from:
   · MP3 player: exchange songs
   · Mass storage: upload/download songs
· Oscilloscope to/from:
   · Printer: print screen image
· Personal digital assistant to/from:
   · Personal digital assistant: exchange files
   · Printer: print files
   · Mobile phone: upload/download files
   · MP3 player: upload/download songs
   · Scanner: scan pictures
   · Mass storage: upload/download files
   · Global Positioning System (GPS): obtain directions, mapping information
   · Digital still camera: upload pictures
   · Oscilloscope: configure oscilloscope

Pinout

Connection Diagram

Specifications

Symbol	Parameter	Conditions	Min	Max	Unit
V_CC(I/O)	supply voltage		-0.5	+4.6	V
V_CC(5V0)	supply voltage		-0.5	+5.6	V
V_{CC(C_IN)}	supply voltage			4.5
I_lu	latch-up current	V_I< 0 or V_I> _VCC	-	100	mA
V_esd	electrostatic discharge voltage	I_LI < 1 A	-4000	+4000	V
T_stg	storage temperature		-40	+125

Description

The ISP1761 is a single-chip Hi-Speed Universal Serial Bus (USB) On-The-Go (OTG) Controller integrated with the advanced Philips Slave Host Controller and the Philips ISP1582 Peripheral Controller.

The Hi-Speed USB Host Controller and Peripheral Controller comply to Universal Serial Bus Specification Rev. 2.0 and support data transfer speeds of up to 480 Mbit/s. The Enhanced Host Controller Interface (EHCI) core implemented in the Host Controller is adapted from Enhanced Host Controller Interface Specification for Universal Serial Bus Rev. 1.0. The OTG controller is compliant with On-The-Go Supplement to the USB Specification Rev. 1.0a.

The ISP1761 has three USB ports. Port 1 can be configured to function as a downstream port, an upstream port or an OTG port; ports 2 and 3 are always configured as downstream ports. The OTG port can switch its role from host to peripheral, and peripheral to host. The OTG port can become a host through the Host Negotiation Protocol (HNP) as specified in the OTG supplement.

ISP1761

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