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Part Number: K4D623238B-GC
Description: The K4D623238 is 67,108,864 bits of hyper synchronous data rate Dynamic RAM organized as 2 x1,048,976 ...
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K4D623238B-GC
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General Description
K4D623238B-GC General Description
The K4D623238 is 67,108,864 bits of hyper synchronous data rate Dynamic RAM organized as 2 x1,048,976 words by 32 bits, fabricated with SAMSUNG 's high performance CMOS technology. Synchronous features with Data Strobe allow extremely high performance up to 2.4GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety of high performance memory system applications.
K4D623238B-GC Maximum Ratings
| Symbol | Symbol | Value | Unit |
| Voltage on any pin relative to Vss | VIN, VOUT | -0.5 ~ 3.6 | V |
| Voltage on VDD supply relative to Vss | VDD | -1.0 ~ 3.6 | V |
| Voltage on VDD supply relative to Vss | VDDQ | -0.5 ~ 3.6 | V |
| Storage temperature | TSTG | -55 ~ +150 | °C |
| Power dissipation | PD | 2.0 | W |
| Short circuit current | IOS | 50 | mA |
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
K4D623238B-GC Features
• 2.5V + 5% power supply for device operation
• VDD/VDDQ = 2.8V ± 5% for -33
• VDD/VDDQ = 2.5V ± 5% for -60/-55/-50/-45/-40
• SSTL_2 compatible inputs/outputs
• 4 banks operation
• MRS cycle with address key programs
-. Read latency 3,4,5 (clock)
-. Burst length (2, 4, 8 and Full page)
-. Burst type (sequential & interleave)
• Full page burst length for sequential burst type only
• Start address of the full page burst should be even
• All inputs except data & DM are sampled at the positive going edge of the system clock
• Differential clock input
• No Wrtie-Interrupted by Read Function
• 4 DQS's ( 1DQS / Byte )
• Data I/O transactions on both edges of Data strobe
• DLL aligns DQ and DQS transitions with Clock transition
• Edge aligned data & data strobe output
• Center aligned data & data strobe input
• DM for write masking only
• Auto & Self refresh
• 16ms refresh period (2K cycle)
• 144-Ball FBGA
• Maximum clock frequency up to 300MHz
• Maximum data rate up to 600Mbps/pin
• VDD/VDDQ = 2.8V ± 5% for -33
• VDD/VDDQ = 2.5V ± 5% for -60/-55/-50/-45/-40
• SSTL_2 compatible inputs/outputs
• 4 banks operation
• MRS cycle with address key programs
-. Read latency 3,4,5 (clock)
-. Burst length (2, 4, 8 and Full page)
-. Burst type (sequential & interleave)
• Full page burst length for sequential burst type only
• Start address of the full page burst should be even
• All inputs except data & DM are sampled at the positive going edge of the system clock
• Differential clock input
• No Wrtie-Interrupted by Read Function
• 4 DQS's ( 1DQS / Byte )
• Data I/O transactions on both edges of Data strobe
• DLL aligns DQ and DQS transitions with Clock transition
• Edge aligned data & data strobe output
• Center aligned data & data strobe input
• DM for write masking only
• Auto & Self refresh
• 16ms refresh period (2K cycle)
• 144-Ball FBGA
• Maximum clock frequency up to 300MHz
• Maximum data rate up to 600Mbps/pin
K4D623238B-GC
PDF/DataSheet Download
- Datasheet: K4D623238B-GC
- File Size: 150898 KB
- Manufacturer: SAMSUNG [Samsung semiconductor]
- Click here to Download
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