Purchase K4H560438E-GCC4, In-stock K4H560438E-GCC4 From SeekIC.
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K4H560438E-GCC4
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DataSheet
General Description
K4H560438E-GCC4 Maximum Ratings
| Parameter | Symbol | Value | Unit |
| Voltage on any pin relative to VSS |
VIN , VOUT |
-0.5 ~ 3.6 | V |
| Voltage on V DD& V DDQsupply relative to VSS |
V DD, VDDQ |
-1.0 ~ 3.6 | V |
| Storage temperature | TSTG |
-55 ~ +150 | |
| Power dissipation | PD |
1.5 | W |
| Short circuit current | IOS |
50 | mA |
K4H560438E-GCC4 Features
* 200MHz Clock, 400Mbps data rate.
* VDD= +2.6V ±0.10V, VDDQ= ±2.6V + 0.10V
* Double-data-rate architecture; two data transfers per clock cycle
* Bidirectional data strobe [DQ] (x4,x8)
* Four banks operation
* Differential clock inputs(CK and CK)
* DLL aligns DQ and DQS transition with CK transition
* MRS cycle with address key programs -. Read latency 3 (clock) for DDR400 , 2.5 (clock) for DDR333 -. Burst length (2, 4, 8) -. Burst type (sequential & interleave)
* All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
* Data I/O transactions on both edges of data strobe
* Edge aligned data output, center aligned data input
* DM for write masking only (x4, x8)
* Auto & Self refresh
* 7.8us refresh interval(8K/64ms refresh)
* Maximum burst refresh cycle : 8
* 60Ball FBGA package
* VDD= +2.6V ±0.10V, VDDQ= ±2.6V + 0.10V
* Double-data-rate architecture; two data transfers per clock cycle
* Bidirectional data strobe [DQ] (x4,x8)
* Four banks operation
* Differential clock inputs(CK and CK)
* DLL aligns DQ and DQS transition with CK transition
* MRS cycle with address key programs -. Read latency 3 (clock) for DDR400 , 2.5 (clock) for DDR333 -. Burst length (2, 4, 8) -. Burst type (sequential & interleave)
* All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
* Data I/O transactions on both edges of data strobe
* Edge aligned data output, center aligned data input
* DM for write masking only (x4, x8)
* Auto & Self refresh
* 7.8us refresh interval(8K/64ms refresh)
* Maximum burst refresh cycle : 8
* 60Ball FBGA package
K4H560438E-GCC4
PDF/DataSheet Download
- Datasheet: K4H560438E-GCC4
- File Size: 202651 KB
- Manufacturer: SAMSUNG [Samsung semiconductor]
- Click here to Download
- ·K4H1G0438A-TCA0
- SAMSUNG [Samsung semiconductor]
- 128Mb DDR SDRAM
- 685336 KB
- ·K4H1G0438A-TCA2
- SAMSUNG [Samsung semiconductor]
- 128Mb DDR SDRAM
- 685336 KB
- ·K4H1G0438A-TCB0
- SAMSUNG [Samsung semiconductor]
- 128Mb DDR SDRAM
- 685336 KB
- ·K4H1G0438A-TLA2
- SAMSUNG [Samsung semiconductor]
- 128Mb DDR SDRAM
- 685336 KB
- ·K4H1G0438A-TLB0
- SAMSUNG [Samsung semiconductor]
- 128Mb DDR SDRAM
- 685336 KB
- ·K4H1G0438B-TCA0
- SAMSUNG [Samsung semiconductor]
- 128Mb DDR SDRAM
- 685336 KB
- ·K4H1G0438B-TCA2
- SAMSUNG [Samsung semiconductor]
- 128Mb DDR SDRAM
- 685336 KB
- ·K4H1G0438B-TCB0
- SAMSUNG [Samsung semiconductor]
- 128Mb DDR SDRAM
- 685336 KB
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