KM44L32031BT-G(F)Z/Y/0

The KM44L32031BT-G(F)Z/Y/0 belongs to 128Mb seriers which are DDR SDRAM specification version 0.61, changed from the earlier version. If you want to know the history of this IC, please go to our website for detail imformation.

The features of KM44L32031BT-G(F)Z/Y/0 can be summarized as (1)double-data-rate architecture; two data transfers per clock cycle; (2)bidirectional data strobe(DQS); (3)four banks operation; (4)differential clock inputs(CK and CK); (5)DLL aligns DQ and DQS transition with CK transition; (6)MRS cycle with address key programs: read latency 2, 2.5 (clock), burst length (2, 4, 8), burst type (sequential & interleave); (7)all inputs except data & DM are sampled at the positive going edge of the system clock(CK); (8)data I/O transactions on both edges of data strobe; (9)edge aligned data output, center aligned data input; (10)ldm,udm/dm for write masking only; (11)auto & self refresh; (12)15.6s refresh interval; (13)maximum burst refresh cycle : 8; (14)66pin TSOP II package.

The absolute maximum ratings of KM44L32031BT-G(F)Z/Y/0 are (1)voltage on any pin relative to VSS VIN, VOUT:-0.5 ~ 3.6V; (2)voltage on VDD supply relative to VSS, VDD, VDDQ: -1.0 ~ 3.6V; (3)voltage on VDDQ supply relative to VSS, VDDQ: -0.5 ~ 3.6V; (4)storage temperature TSTG: -55 ~ +150°C; (5)power dissipation PD: 1.0W; (6)short circuit current IOS: 50mA. (Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommend operation condition.Exposure to higher than recommended voltage for extended periods of time could affect device reliability.)