KM718V887

Features: • Synchronous Operation.• On-Chip Address Counter.• Write Self-Timed Cycle.• On-Chip Address and Control Registers.• VDD= 3.3V+0.3V/-0.165V Power Supply.• VDDQ Supply Voltage 3.3V+0.3V/-0.165V for 3.3V I/O or 2.5V+0.4V/-0.125V for 2.5V I/O.• 5V T...

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SeekIC No. : 004386186 Detail

KM718V887: Features: • Synchronous Operation.• On-Chip Address Counter.• Write Self-Timed Cycle.• On-Chip Address and Control Registers.• VDD= 3.3V+0.3V/-0.165V Power Supply.̶...

floor Price/Ceiling Price

Part Number:
KM718V887
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2019/9/15

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Product Details

Description



Features:

• Synchronous Operation.
• On-Chip Address Counter.
• Write Self-Timed Cycle.
• On-Chip Address and Control Registers.
• VDD= 3.3V+0.3V/-0.165V Power Supply.
• VDDQ Supply Voltage 3.3V+0.3V/-0.165V for 3.3V I/O or 2.5V+0.4V/-0.125V for 2.5V I/O.
• 5V Tolerant Inputs except I/O Pins.
• Byte Writable Function.
• Global Write Enable Controls a full bus-width write.
• Power Down State via ZZ Signal.
• Asynchronous Output Enable Control.
• ADSP, ADSC, ADV Burst Control Pins.
• LBO Pin allows a choice of either a interleaved burst or a linear burst.
• Three Chip Enables for simple depth expansion with No Data Contention.
• TTL-Level Three-State Output.
• 100-TQFP-1420A



Pinout

  Connection Diagram


Specifications

PARAMETER
SYMBOL
RATING
UNIT
Voltage on VDD Supply Relative to VSS
VDD
-0.3 to 4.6
V
Voltage on VDDQ Supply Relative to VSS
VDDQ
VDD
V
Voltage on Input Pin Relative to VSS
VIN
-0.3 to 6.0
V
Voltage on I/O Pin Relative to VSS
VIO
-0.3 to VDDQ+0.5
V
Power Dissipation
PD
1.2
W
Storage Temperature
TSTG
-65 to 150
Operating Temperature
TOPR
0 to 70
Storage Temperature Range Under Bias
TBIAS
-10 to 85



Description

The KM718V887 is a 4,718,592 bit Synchronous Static Random Access Memory designed for support zero wait state performance for advanced Pentium/Power PC address pipelining. And with CS1 high, ADSP is blocked to control signal.

The KM718V887 is organized as 256K words of 18 bits and integrates address and control registers, a 2-bit burst address counter and high output drive circuitry onto a single integrated circuit for reduced components count implementation of high performance cache RAM applications.

Write cycles are internally self-timed and synchronous.

The self-timed write feature eliminates complex off chip write pulse shaping logic, simplifying the cache design and further reducing the component count.

Burst cycle can be initiated with either the address status processor( ADSP) or address status cache controller(ADSC) inputs. Subsequent burst addresses are generated internally in the system¢s burst sequence and are controlled by the burst address advance(ADV) input. ZZ pin controls Power Down State and reduces Stand-by current regardless of CLK.

The KM718V887 is implemented in SAMSUNG¢s high performance CMOS technology and is available in a 100pin TQFP package. Multiple power and ground pins are utilized to minimize ground bounce.




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