LC822152

• CCD/CMOS Interface YUV422 (8-bit) format. Maximum VGA size : 640*480.
       MCKI : System clock supplied to the CCD/CMOS module.
       PCLK : Dot clock output from the CCD/CMOS module.
• CPU Interface 80-system 16-bit bus (D15-D0, WR, RD, A2-0, CS) Accessible to the JPEG controller, control register including I²C master, JPEG code buffer,thumbnail image buffer, OSD display buffer, and LCD command buffer.
•  LCD Interface Connects the chip to the LCD controller system bus with the 80-system 16-bit bus interface.
   It is accessible by switching automatically the two masters, host CPU or LSI imageprocessing unit. Output image from LSI is RGB565 (16-bit) or RGB666 (18-bit, 9-bit*2, etc.). Maximum display size is 320*240 (without OSD) or 320*200 (with OSD). Camera image display to the sub LCD is possible.
• I²C Interface Built-in I²C master for CCD/CMOS module control. Without paying attention to the I²C from the CPU, it is accessible to the CCD/CMOS module as well as the normal register (write/read).
• Scaling function CCD output is a VGA size (640*480). The output is reduced/cropped to meet the LCD
display range with a scaler. Low-pass filter and enhancer are equipped.
• JPEG codec The YUV422/YUV420 image data is compressed into JPEG code, and the JPEG code data is expanded to the YUV422/YUV420 image data.
• Thumbnail It performs thinning out, scaling down and cropping the LCD output images to an image size of maximum 40*40.
• Clock system LSI includes PLL and it multiplies the clock input from outside to make a main clock.It divides this multiplied frequency to output to CCD/CMOS module as the clock.
• Package FBGA96K
• Process 0.18m E/A
• Power source voltage Internal 1.8V±0.18V, I/O 3.0V±0.3V